Experiment#8 Sequential Logic Circuits

Experiment #8

Latches and Flip-Flops characteristics

Clock generator circuits

OBJECTIVES

To be familiarized with D and JK flip-flop ICs and their characteristic tables.
Understanding the principles and construction of Clock generator.

Background

Flip-flops are a useful type of digital device that can store binary states, or be used as a sort of digital toggle switch. Flip-flops can be built up from distinct logic gates, but they can easily be bought in packaged chips. The flip-flop is a digital device, so its output (labeled with a Q in schematic diagrams) will take on the value of either 1 (high) or 0 (low). Many flip-flops will also provide the complementary output (an inverted output).

Edge Triggering

Because the state of a flip-flop often depends on the previous state of a circuit (for example, the output of one flip flop may be the input to another), and because each flip-flop and logic gate needs a certain amount of time to switch its output, we usually clock the devices, that is, we synchronize all the flip-flops to change states at the same time with a clocked pulse. Flip-flops are edge triggered; they either change states when the clock goes from 0 to 1 (positive/rising edge) or when the clock goes from 1 to 0 (negative/falling edge).

The symbols used for positive and negative edge triggering on flip-flops are shown in fig.10.1:

Asynchronous Inputs

Many flip-flops will also have a clear (CLR) and preset (PRE) terminal. These inputs are typically inverted, so they are active when the input signal is low (Active Low Input). The CLR and PRE signals can be asserted any time and don't have to be edge triggered; they will override any other inputs, including the clock.

The symbols used for clear and preset (the bubble indicates an inverted signal) are shown in figure 10.2.

Truth Table for CLR and PRE (active low)
PRE / CLR / Output
0 / 0 / Error state
0 / 1 / 1
1 / 0 / 0
1 / 1 / Depends on inputs and clock

Types of flip-flops

There are several types of flip-flops but the two most important kind are the D and J-K flip-flops.

D flip-flop

D / ClK / Q
0 / ↑ / 0
1 / ↑ / 1
X / 0,1 / Q0

Symbol for the D flip-flop is shown in figure 10.3.The D (Data) flip-flop has an input D, and the output Q will take on the value of D at every triggering edge of the clock pulse and hold it until the next triggering pulse.The D flip-flop is usually positive edge triggered. The truth table for a positive edge triggered D flip-flop in table 10.1:

(↑ indicates a rising edge on the clock pulse; X indicates that it has no effect on outcome) Timing diagram for the positive edge triggered D flip-flop:

The TTL 7474 is a dual (has two) D type flip-flop.

JK flip-flop

Symbol for the JK flip-flop is shown in figure 10.4. The JK flip-flop has two inputs, labeled J and K. J corresponds to a "set" signal, and K corresponds to a "reset" signal. At the triggering edge:

If J is 1 and K is 0, Q is 1. If J is 0 and K is 1, Q is 0. If J and K are both 0, the output stays the same as it was before. If J and K are both 1, the output is inverted (toggling is said to occure). The JK flip-flop is usually negative edge triggered. The truth table for a negatively triggered JK flip-flop:

J / K / CK / Q
0 / 0 / ↓ / Q0
0 / 1 / ↓ / 0
1 / 0 / ↓ / 1
1 / 1 / ↓ / Q'0
X / X / 0,1 / Q0

The timing diagram for the negatively triggered JK flip-flop:

The TTL 7476 is a dual (has two) J-K type flip-flop.

Latches

Latches are similar to flip-flops, but instead of being edge triggered, they are level triggered. The most common type of latch is the D latch. While CK is high, Q will take whatever value D is at.When CK is low, Q will latch onto the last value it had before CK went low, and hold it until CK goes high again. Timing diagram for the D latch:

The 7475 is a 16 pin 4 bit binary D-latch and is generally used to temporarily store information. The inputs are labeled 1D-4D and both the outputs and their complements are available on this 16-pin chip. Because of pin limitations, latches 1 and 2 are controlled by the same enable signal and latches 3 and 4 are controlled by the other enable signal.

Clock Generator

Timing or synchronization is very crucial to most electronic devices and systems. This is because timing is essential in maintaining the proper sequencing of events. There are many ICs designed and manufactured specifically to accomplish this task. One of the most popular of these ICs is the 555 Timer. Figure 10.5 shows the pin diagram of the 555 Timer IC.

The 555 timer can be used in a variety of forms. The monostable mode will create a single pulse of a specified width. Astable mode will create a repeating pulse train of specified frequency and duty cycle.

Figure 10.6 shows the 555 IC Timer configured to output a clock signal.

The charging time (output high) is given by:

t high = 0.693*(R1 + R2)*C

And the discharging time (output low) by:

t low = 0.693*(R2)*C

Thus the total period is:

T = t high + t low = 0.693*(R1 + 2*R2)*C

The clock frequency is determined by the formula:

F = 1/T = 1.44/((R1 + 2*R2)*C)

Sequential Circuits

Synchronous sequential circuits use logic gates and flip-flop storage devices. Sequential circuits have a clock signal as one of their inputs. All state transitions in such circuits occur only when the clock value is either 0 or 1 or happen at the rising or falling edges of the clock depending on the type of memory elements used in the circuit. Synchronization is achieved by a timing device called a clock pulse generator. Clock pulses are distributed throughout the system in such a way that the flip-flops are affected only with the arrival of the synchronization pulse. Synchronous sequential circuits that use clock pulses in the inputs are called clocked-sequential circuits. They are stable and their timing can easily be broken down into independent discrete steps, each of which is considered separately.

For example consider the following circuit:

Prelab

Study the background carefully.
Use data sheet to draw the schematic (pin diagram) of the 7475 adual d type latchand write down its function table.
Use data sheet to draw the schematic (pin diagram) of the 7474 a dual d type Flip-Flopand write down its function table.
Use data sheet to draw the schematic (pin diagram) of the 7476 a dual JK type Flip-Flopand write down its function table.
Derive the state table, state diagram, and clock diagram for the sequential circuit in fig. 8.7, and draw circuit connection in schematic diagram.

EQUIPMENTS REQUIRED

KL-31001 trainer kit,Module KL-33007, TTL ICs 7474, 7475, and 7476.

PROCEDURES:

Part I: D type Latch

a)Plug in the 74LS74 D-type flip-flop and connect ground to pin 7 and 5V to pin 14 as usual.Referring to the 74LS75 pin-out diagram, choose one of the four D latches on the chip and connect the input switches to the D and C.

b)Set input C to 0, set input D to 1 and then to 0 several times. What is the result?

c)Repeat step b, but at this time set input C to 1. What is the result?

d)Verify the function table of 7475.

Part II: D type Flip-Flop

a)Plug in the 74LS74 D-type flip-flop and connect ground to pin 7 and 5V to pin 14 as usual. This is a two-circuit dual in-line package. Referring to the 74LS74 pin-out diagram, choose one of the two D FFs on the chip and connect the input switches to the D,cleare and Preset inputs(CLR and PR). Connect the Clock input tothe pulse switch. The Q and Q' outputs should be connected to LEDs.

b)Set Clear to 0 and Preset to 1, set D input to 1 and toggle the clock pulse. Is the result in Q going to 1 or not why?

c)Set Clear to 1 and Preset to 0,what is the output?. Set D input to 0 and toggle the clock pulse. Is the result in Q going to 1 or not why?

d)Set Clear to 1 and Preset to 0 simultaneouslythis will result in both Q and Q going to 1 (both LEDs will light). This is a forbidden state.

e)Try the various inputs (Clock with D, Preset, Clear) and observe the circuit operation. Verify the truth table you have written in your prelab step3.

Part III: J-K type Flip-Flop

a)Plug in the 74LS76JK-type flip-flop and connect ground to pin 13 and 5V to pin 5. This is a two-circuit dual in-line package. Referring to the 74LS76 pin-out diagram, choose one of the two JK FFs on the chip and connect the input switches to the D , clearand Preset inputs (CLR and PR). Connect the Clock input tothe pulse switch . The Q and Q' outputs should be connected to LEDs.

b)Test the effect of CLR and PR on the circuit as in part 2.Try various inputs (Clock with J and K, Preset, Clear) and verify the truth table you have written in your prelab step 4.

Part IV: Clock generation with 555 IC Oscillator circuit

a)Module KL-33007will be used in this part.

b)Insert connection clips according to figure 8.8(a) to get equivalent circuit shown in figure 8.8(b)

c)Connect F1 to LED and observe the output.

d)Adjust R9 an R12 and state how the output is affected by them.

Part V: Sequential Circuit

a)Connect the circuit you have drawn in prelab step 5, verify the state diagram of the circuit.

Exercise:

1)If you need to use a J-K FF, but the 7476 IC is not available but 7474 IC is available. Build a J-K FF using D FF, show your circuit in logic and pin diagrams.

2)If you need to use a D FF, but the 7474 IC is not available but 7476 IC is available. Build a D FF using J-K FF, show your circuit in logic and pin diagrams.