Experiment 6
Shift Registers
Backgound
(July 1, 2003)
These notes give some background on NAND gates, set-reset flip-flops, data flip-flops, shift registers and CMOS inverters.
NAND gates
A NAND gate is drawn schematically as
A type 7401 NAND is frequently used in this lab. The truth-table for a NAND gate is described by
A
/ B / AND / NAND0 / 0 / 0 / 1
0 / 1 / 0 / 1
1 / 0 / 0 / 1
1 / 1 / 1 / 0
Thus the output from the NAND gate is 0 if and only if the two inputs are one.
Set-reset flip flops
We can make a set-reset flip-flop from NAND gates by cross-coupling two gates. The appropriate arrangement is
Let’s examine the output of the S-R flip-flop for several pairs of inputs. The circuit is easily analyzed if we recall that the output from the NAND is 0 i.f.f. both inputs are 1.
- If R =1 and S = 0
_
a)Q = 1
b) “a” = 1
c) the output from the top gate = 0 and Q = 0
- If R = 0 and S = 1 similar logic leads to the conclusion that
_
Q = 0 and Q = 1.
3. The situation is more complicated if R = 1 and S = 1. In that case the output from the flip-flop depends on its previous state. Once again recall that
the output from the NAND is 0 i.f.f. both inputs are 1.
Assume that the present state of the flip-flop is characterized by
_
Q = 1 and Q = 0.
Then the two inputs to the top NAND gate are 1 and the output Q = 0.
The output from the top flip-flop is cross-coupled to the “b” input of the bottom NAND gate and the output from the bottom NAND gate is given by
_
Q = 1.
and the original state of the flip-flop is maintained.
_
If R=S=1 and Q = 1 and Q = 0 similar reasoning leads to the conclusion that the
_
original state Q = 1 and Q = 0 is maintained.
The inputs R = S = 0 leads to instabilities in the output of the flip-flop and is not used.
Data flip-flops
A common variety of flip-flop is a clock-enabled, data flip-flop (D-FF). This flip-flop is shown schematically as
If the clock is 0 then the circuit exhibits memory and the outputs do not change in response to changes in D. If the clock input in a logical 1 then the output Q acquires the value of D. A D-FF can be implemented by using four NAND gates.
The appropriate circuit is shown below
The Clock input is denoted CL.. If CL = 0 then the outputs of the first (left-hand) set of NAND gates are 1. This means the inputs to the second set of NAND
_
gates (labeled R and S) are 1 and the output Q and Q are maintained.
If CL = 1 then the outputs from the second set of NAND gates can change and these outputs will follow D.
Shift registers
A shift register is a digital memory device in which data are loaded serially, one bit at a time. The simplest and most common implementation of a shift register is constructed by connecting a series a D flip-flops, in which the Q output of each stage feeds the D input of the next. The figure below shows a four-bit shift register built in this fashion.
Four-Bit Shift Register
Data are loaded into the shift register from the left, and for each rising edge on the clock signal, all bits shift one position to the right. In order to load the register with data, the data input signal must be synchronized with the clock, and four clock cycles are required to load all four bits.
Shift registers are found in a variety of digital and analog applications. Perhaps the most widely used of these is in digital filtering, where bits representing samples of an analog signal are shifted through the register. By connecting appropriate logic gates or resistor networks to the shift register outputs, the desired filtering operation can be achieved. Since a full understanding of how such filters work is beyond the scope of this course, we will not consider them here (this topic is covered in EE 1563).
CMOS inverters
CMOS inverters (Complementary MOSFET Inverters) are some of the most widely used and adaptable MOSFET inverters used in chip design. A CMOS inverter contains a PMOS and a NMOS transistor connected at the drain and gate terminals, a supply voltage VDD at the PMOS source terminal, and a ground connected at the NMOS source terminal, were VIN is connected to the gate terminals and VOUT is connected to the drain terminals (see diagram below). When VIN is low, the NMOS is "off", while the PMOS stays "on": instantly charging VOUT to logic high. When VIN is high, the NMOS is "on and the PMOS is "off": draining the voltage at VOUT to logic low.
Updated on March 23, 2017