Drexel University
Electrical and Computer Engineering
ECE-C302 Midterm October 30, 2006
Name _Solution__
Problem 1: Code a 4-bit adder
Entity adder_4 is
Port ( X, Y : in std_logic_vector(3 downto 0);
Cin : in std_logic;
Z : out std_logic_vector(3 downto 0);
Cout : out std_logic);
End adder_4;
Architecture beh of adder_4 is
Begin
Process(x,y,cin)
Variable carry : std_logic;
Begin
Carry := Cin;
For I in 0 to 3 loop
Z(i) <= X(i) xor y(i) xor carry;
Carry := (X(i) and Y(i)) or (carry and Y(i)) or (X(i) and carry);
End loop;
Cout <= carry;
End process;
End beh;
Problem 2: Design a controller for an architecture below
Entity controller is
Port (go, reset, ck : in std_logic;
ldA, ldB, ldC, en, drC : out std_logic);
end controller;
The control steps
1. idle, when go=’1’ go to Step 2 (all signals disable)
2. load Register A by assigning ldA <= ‘1’, (other signals disable)
3. load Register B
4. enable Unit M for 10 clock cycles then go to Step 5
5. load Register C
6. Register C drives the bus by drC <= ‘1’ and go to Step 1
All control signals are active high. When reset = ‘1’ the controller goes to Step 1.
Architecture beh of controller is
Type my_state is (s1,s2,s3,s4,s5,s6);
Signal ns : my_state;
Begin
Process(ck)
Variable count : interger;
Begin
If ck = ‘1’ and ck’event then
If reset=’1’ then n_s <= s1; count := 0; Elsif reset = ‘0’ then
Case n_s is
When s1 => ldA<=’0’; ldB<=’0’; ldC<= ‘0’; drC <=’0’; en <= ‘0’;
If go = ‘1’ then n_s <= s2;
When s2 => ldA<=’1’; ldB<=’0’; ldC<= ‘0’; drC<=’0’; en <= ‘0’;n_s <= s2;
When s3 => ldA<=’0’; ldB<=’1’; ldC<= ‘0’; drC<=’0’; en <= ‘0’;n_s <= s4;
When s4 => ldA<=’0’; ldB<=’0’; ldC<= ‘0’; drC<=’0’; en <= ‘1’;
Count := count + 1; If count = 10 then n_s <= s5;
When s5 => ldA<=’0’; ldB<=’0’; ldC<= ‘1’; drC<=’0’; en <= ‘0’;n_s <= s6;
When s6 => ldA<=’0’; ldB<=’0’; ldC<= ‘0’; drC<=’1’; en <= ‘0’;n_s <= s1;
End case; end if; end if; end process; end beh;