ECS Interface Library User Guide
1MHz version
Version: Release_v2.4.4
Last modified: 1.12.2007
Prepared by: Hui Gong, Alex Gong, Hou Lei, Dai Gang and Guido Haefeli
Note that this document is strongly related to the TELL1 firmware version!
Document status sheet
Revision / Date / Changes made2.4.4
2.4 / 20.3.2006
5.3.2008 / Improoved parity checking and CRC checking on the QDR
Added the low threshold for Velo per strip
Added the FIR coefficients for Velo
Added header correction value per link
Added MCMS enable bit for Velo
ST and VELO header_corr_value link wise, header_corr_threshold per board
ST spill_over_threshold, confirmation_threshold instead of sum_th, there is one value per processor channel (2 per Beetle)
Add parity check error counter for LLink and QDR
Add parity error cnt for Trigger info links
Added pp_error_mon and sl_error_mon registers
2.3
2.1.1 / 30.11.2007
5.9.2007 / Add last sent Dest IP sent by ttc register 0x10010AC
Add test reg in PPs and SL 0x4000010, 0x100001C
Add ecs_error_cnt regs again for PP and SL
Add L0CAL, add PP used as common parameter,
1.9 / 15.1.2007 / Add MUON memory space.
Upgrade PP_CTRL_REG1 and MEM_MAX_USAGE_REG2
Change Calo VHDL detector ID to distinguish ECAL/HCAL and PS/SPD
1.8 / 28.9.2006 / Fixed inversed long/short counter for the O-Rx Probe reg
Changed default value for O-Rx links to be disabled
1.7 / 09,08,2006 / Add OT memory space
Maximum memory usage register adjusted.
1.6 / 17.7.2006
1.5 / 29.6.2006 / Separate the ECS vhdl manual from the register and memory map,
Update the ecs implementation to the current version! The ecs_reg register array is not available anymore in the components and registers.
ECS Interface Library User Guide 1
1MHz version 1
Version: Release_v2.3 1
Document status sheet 2
1. Memory MAP 7
2. Registers and RAM for “PP” 7
2.1 Common Registers 7
PP_RESET_REG ($0x000000) 7
PP_CTRL_REG0 ($0x000004) 8
PP_CTRL_REG1 ($0x000008) 8
ORX_CTRL REG ($0x00000C) 9
PPTEST_REG ($0x000010) 10
2.2 Common Monitor registers 10
CONSTANT_REG ($0x001000) 10
EVT_ASSEM_CNT_REG ($0x001004) 11
PP_TRIGGER_CNT_REG ($0x001008) 11
PP_BANK_CNT_REG0 ($0x00100C) 11
PP_BANK_CNT_REG1 ($0x001010) 11
PP_EVENT_CNT_REG ($0x001014) 11
BER_ERROR_CNT_REG ($0x001018) 12
BER_RCV_CNT_H_REG ($0x00101C) 12
BER_ RCV_CNT_L_REG ($0x001020) 12
INFO_PARITY_ERROR_CNT_REG ($0x001024) reg9 12
PP_ERROR_MON_REG ($0x001028) 12
PP_ECS_ERROR_CNT_REG ($0x00102C) 13
PP_DATE_REG ($0x001034) 13
PP_TIME_REG ($0x001038) 13
PP_VERSION_REG ($0x00103C) 13
ORX_PROBE_REG ($0x001040) 13
ORX_ SYNC_REG ($0x001044) REALTIME 14
ORX_ LINK_DISABLE_REG ($0x001048) 15
FIFO_STATUS_REG ($0x00104C-($0x00104C…0x00104C +11*4) 15
2.3 User Specific Register VELO (starts from 0x002000) 15
VELO_ADCCLK_PHY_DLY_REGH ($0x002000) 15
VELO_ADCCLK_PHY_DLY_REGL ($0x002004) 16
VELO_ADCCLK_CYC_DLY_REG ($0x002008) 16
9 CLUS_PARA_REG ($0x00200C, $0x002010 …$0x00202C) 16
ADC_LINK_PROBE_REG ($0x002030) 17
ADC_LINK_SYNC_REG ($0x002034) 17
VELO_PHI_REORDER_STRIP_CNT_REG ($0x002038) 18
VELO_HEADER_CORR_THRESHOLD_REG ($0x00203C) 18
VELO_CLUSTER_NUMBER_MAX_REG ($0x002044) 18
VELO_FIR_COEFFICIENT_REG ($0x002048 …($0x002064 ) 18
8 Registers last is register 26 18
VELO_HEADER_CORR_VALUE_REG ($0x002068-$0x002084) 8 registers 19
8 Registers last is register 24 19
VELO_FIFO_STATUS_REG (access via common monitor registers) 12 registers 19
2.4 User Specific Register ST (starts from 0x003000) 20
12 CLUS_PARA_REG ($0x003004, $0x003008 …$0x003030) 20
Removed register for optical links, they are common registers now ! 20
ST_HEADER_CORR_THRESHOLD_REG ($0x00303C) 20
ST_CLUSTER_NUMBER_MAX_REG ($0x003044) 20
ST_HEADER_CORR_VALUE_REG ($0x003048-$0x003074) 12 registers 20
ST_FIFO_STATUS_REG (access via common monitor registers) 12 registers 20
2.5 User Specific Register OT (starts from 0x004000) 21
6 OT_OTIS_CTRL_REG ($0x004000 ~ $0x004014) 21
OT_OTIS_STATUS_AB_REG ($0x004018) 21
OT_OTIS_STATUS_CD_REG ($0x00401C) 21
OT_ZS_LINKER_ERROR_V_REG($0x004020) 21
2.6 User Specific Register MUON (starts from 0x006000) 22
6 MUON_TU_TYPE_REG ($0x006000 ~ $0x006014) 22
MUON_HIT_PAD_PROC_CTRL_REG ($0x006018) 22
MUON_ODE_ID_REG1 ($0x00601C) 23
MUON_ODE_ID_REG2 ($0x006020) 23
MUON_ODE_ID_REG3 ($0x006024) 23
MUON_PAD_MAX_NUM_REG ($0x006028) 24
MUON_HIT_MAX_NUM_REG ($0x00602C) 24
MUON_FIFO_STATUS_REG (access via common monitor registers) 12 registers 24
2.6’ User Specific Register L0MUON (starts from 0x00C000) 25
PP_L0MUON_CTRL_REG ($0x00C000) 25
6 ORX_CONNECTIVITY_TEST_DATA_REG ($0x00C018 ~ $0x00C02C) 25
2.7 User Specific Register EHCAL (starts from 0x005000) 25
CAL_CTRL_REG ($0x005000) 25
EHCAL_FIFO_STATUS_REG (access via common monitor registers) 13 registers 25
2.7’User Specific Register L0CAL (starts from 0x00A000) 26
PP_L0CAL_PARA_REG ($0x00A000) 26
L0CAL_FIFO_STATUS_REG (access via common monitor registers) 12 registers 26
2.8 User Specific Register RICH (starts from 0x009000) 27
RICH_FIFO_STATUS_REG (access via common monitor registers) 12 registers 27
2.9 User Specific Register L0PUS (starts from 0x008000) 27
L0PUS_FIFO_STATUS_REG (access via common monitor registers) 12 registers 27
2.10 User Specific Register BCM (starts from 0x00C000) 28
BCM_FIFO_STATUS_REG (access via common monitor registers) 12 registers 28
2.11 Common RAM blocks 29
DATA_GEN_RAM SectionA (Address range: 0x100000 – 0x1001FF) 29
DATA_GEN_RAM SectionB (Address range: 0x102000 – 0x1021FF) 29
DATA_GEN_RAM SectionC (Address range: 0x104000 – 0x1041FF) 29
DATA_GEN_RAM SectionD (Address range: 0x106000 – 0x1061FF) 30
DATA_GEN_RAM SectionE (Address range: 0x108000 – 0x1081FF) 30
DATA_GEN_RAM SectionF (Address range: 0x10A000 – 0x10A1FF) 30
2.12 User Specific RAM blocks VELO (starts from 0x200000) 31
8 PEDESTAL RAM (Address range: 0x200000 – 0x2000FF, 0x202000-0x2020FF,….,, 0x20E000 - 0x20E0FF) 31
9 THRESHOLD RAM (Address range: 0x210000–0x2100FF, 0x212000-0x2120FF, … , 0x220000-0x2200FF) 32
VELO_AVERAGE_HISTOGRAM (Address range: 0x234000–0x237FFF) ram26 32
VELO_SLOPE_HISTOGRAM (Address range: 0x238000–0x23BFFF) –ram28 32
8 VELO_REORDER_RAM (Address range: 0x23C000–0x23C0FF, … , 0x24A000–0x24A0FF) reserve 32
2.13 User Specific RAM blocks ST (starts from 0x300000) 33
12 PEDESTAL RAM (Address range: 0x300000 – 0x3000FF, 0x302000-0x3020FF,….,, 0x316000 - 0x3160FF) 33
12 HIT_THRESHOLD RAM (Address range: 0x318000 – 0x3180FF, 0x31A000-0x31A0FF,….,, 0x32E000 - 0x32E0FF) 33
12 CMS_THRESHOLD RAM (Address range: 0x330000 – 0x3300FF, 0x332000-0x3320FF,….,, 0x346000 - 0x3460FF) 33
1 ST_AVERAGE_HISTOGRAM (Address range: 0x348000– 0x349800) –ram36 33
1 ST_SLOPE_HISTOGRAM (Address range: 0x34C000–0x34D800) –ram38 34
2.14 User Specific RAM blocks OT (starts from 0x400000) 34
12 OT_HITNUM_HISTOGRAM (Address range: 0x4400000–0x4416000) 34
12 OT_Drift_time_HISTOGRAM (Address range: 0x4418000–0x442E000) 34
3. Registers and RAM for “SyncLink” 35
3.1 Common control registers 35
SL_RESET_REG ($0x000000) 35
SL_CTRL_REG0 ($0x000004) 35
SL_CTRL_REG1 ($0x000008) 37
SL_SIMU_CTRL_REG ($0x00000C) 37
SPI3_TX_CTRL_REG ($0x000010) 38
SPI3_RX_CTRL_REG ($0x000014) 39
THRO_CTRL_REG ($0x000018) 39
SLTEST_REG ($0x00001C) 39
MEP_PID_REG ($0x000020) 39
ECS_SIMU_TRIG_NUM_REG ($0x000024) 39
ECS_SIMU_TRIG_SCHE_REG ($0x000028) 40
SEP_MSB4_REG ($0x00002C) 40
PEDESTAL_BANK_SCHEDULE_CTRL_REG ($0x000030) 40
BANK_HEADER2_REG ($0x000034) 40
SL_TP_REG ($0x000038) 41
MTU_SIZE_REG ($0x00003C) 41
BANK_CLASS_REG ($0x000040) 42
3.2 Common monitor registers 42
SL_PP_PROB_REG ($0x001000) 42
SL_EVT_CNT_REG ($0x001004) 42
SL_EVT_OUT_CNT_REG ($0x001008) 42
LLINK_PARITY_ERROR_CNT_REG($0x00100C) 42
SPI3_TX_MEP_CNT_REG ($0x001010) 43
SPI3_TX_WORD_CNT_REG ($0x001014) 43
SPI3_TX_SOP_CNT_REG ($0x001018) 43
SPI3_TX_EOP_CNT_REG ($0x00101C) 43
TTC_TRIG_CNT_REG ($0x001020) REALTIME 43
TTC_TRIG_TYPE_CNT_REG ($0x001024) REALTIME 43
TTC_DEST_IP_CNT_REG ($0x001028) REALTIME 44
TTC_RESET_SIG_CNT_REG ($0x00102C) REALTIME 44
SL_TRIG_CNT_REG ($0x001030) REALTIME 44
TRIG_INFO_TX_CNT_REG ($0x001034) REALTIME 44
TRIG_INFO_REQ_CNT_REG ($0x001038) REALTIME 44
TRIG_INFO_FIFO_MON_REG0 ($0x00103C) REALTIME 44
TRIG_INFO_FIFO_MON_REG1 ($0x001040) REALTIME 45
MEP_WRITE_CNT_REG ($0x001044) 45
MEP_READ_CNT_REG ($0x001048) 46
MEP_MAX_USAGE_REG ($0x00104C) 46
SL_ERR_LOG_REG ($0x001050) 46
SL_MAX_USE_REG ($0x001054) 47
FROZEN_EVID_REG ($0x001058) REALTIME 48
FROZEN_BCNT_REG ($0x00105C) REALTIME 48
FRAMER_MAX_USE_REG ($0x001060) 48
REAL_RATE_REG0 ($0x001064) 48
REAL_RATE_REG1 ($0x001068) 49
REAL_RATE_REG2 ($0x00106C) 49
REAL_RATE_REG3 ($0x001070) 49
REAL_RATE_REG4 ($0x001074) 49
SL_FLOWCTRL_MONITOR_REG ($0x001078) 49
MEP_GT_16K_CNT_REG ($0x00107C) 50
SL_DATE_REG ($0x001080) 50
SL_TIME_REG ($0x001084) 50
SL_VERSION_REG ($0x001088) 50
SL_TRIGGER_FIFO_USED_REG0 ($0x00108C) 51
SL_TRIGGER_FIFO_USED_REG1 ($0x001090) 51
SL_FEM_DV_CNT_REG ($0x001094) REALTIME 51
SL_DEST_IP_L0_EVID_LSB_ERROR_CNT_REG ($0x001098) 51
THRO_CNT_REG0 ($0x00109C) –REG39 51
THRO_CNT_REG1 ($0x0010A0) 52
THRO_CNT_REG2 ($0x0010A4) 52
THRO_CNT_REG3 ($0x0010A8) 52
SL_TTC_LAST_DEST_IP_REG ($0x0010AC) 52
SL_LBUS_TEST_REG ($0x0010B0-$0x0010CC) 8 x 32-bit 52
QDR_PARITY_ERROR_CNT_REG $0x0010D0) reg52 53
SL_ERROR_MON_REG $0x0010D4) reg53 53
3.3 Common RAM blocks 53
MEP_LOCATION_RAM (Address range: 0x100000 – 0x1001FF) 53
IPv4_HEADER_RAM (Address range: 0x102000 - 0x1020FF) 54
INTEL_MAC_LPB_TX_RAM (Address range: 0x104000 - 0x1043FF) 56
INTEL_MAC_LPB_RX_RAM (Address range: 0x106000 – 0x1063FF) 57
SEP_GEN_RAM (Address range: 0x200000 – 0x20FFFF) 57
4. I2C bus address definition 57
I2C BUS 0 (mixed) 57
I2C BUS 1 (FPGA bus) 58
I2C BUS 2 (A-Rx DAC bus) 58
I2C BUS 3 (GBE Tx card bus) 59
Appendix: Example codes for C access 59
1. Memory MAP
Base address:
SyncLink = 0x1000000; PP0 = 0x4000000 ; PP1 = 0x5000000; PP2 = 0x6000000; PP3 = 0x7000000
2. Registers and RAM for “PP”
2.1 Common Registers
The common register region is divided into two parts as control registers part and monitor registers part. The former is used to provide external control/setting signals to the internal TELL1 logic, they are read/write. The latter is used to read out the TELL1 self-generated information like counters, error information, etc. They are read only.
PP_RESET_REG ($0x000000)
Bit / Name / Description / Type / DefaultRegister Description: One cycle@40MHz after written, the register will return to its default value. Used to generate pulses. / 0x00000000
31- 8 / N
7 - 2 / RESERVE0
1 / BER_CNT_RESET / Clear all BER relative counters / W / 0
0 / ADC_CLK_RESET / Re-initial all adc_clk phase / W / 0
R = Read Only; W = Write; R/W = Read/Write; N = Not exist;
PP_CTRL_REG0 ($0x000004)
Bit / Name / Description / Type / DefaultRegister Description: Provide common and basic control signals for PP process. / 0xA0900204
31-24 / PSEUDO_BIT_H_THR / High threshold for generate the pseudo header bits. ADC values higher than this value is treated as logic ‘1’. / R/W / 0xA0
23-16 / PSEUDO_BIT_L_THR / Low threshold for generate the pseudo header bits. ADC values lower than this value is treated as logic ‘0’. / R/W / 0x90
15-12 / READ_LINK_SEL / The monitor registers for each link share the same ECS address, this field is used to select a certain link’s register to read out.( 0-15 for ARX, 0-5 for ORX) / R/W / 0
11 / R_reorder / Choose the R-sensor reordering for VELO / 0
10 / PHI_reorder / Choose the Phi-sensor reordering for VELO / 0
9 / ZS_EN / Enable/disable the zerosuppression suppression / 1
8 / LCMS_EN / Linear CM suppression after re-ordering Enable/disable the common mode suppression / 0
7 / BER_EN / Enable/Disable the Bit Error Rate test function ( For ORX only) / R/W / 0
6 / DATA_GEN_EN / Enable/Disable the internal data generator to replace the actually detector data / R/W / 0
5 / FIR_EN / Enable/disable the FIR ( ARX only) / R/W / 0
4 / REORDER_EN / (VELO only) / R/W / 0
3 / PEDESTAL_UPDATE_EN / Enable/Disable the pedestal auto update feather, with which the pedestal can follow up the base line shift. / R/W / 0
2 / PEDESTAL_EN / Enable/Disable the pedestal subtraction / R/W / 1
1-0 / DATA_SCALE_MODE / After pedestal subtraction, determines how to scale the 11bit down to 8bit
0: saturate to -128 to 127 (VELO only)
1: bit(8..1) (LSB remove)
2: bit(9..2) (2LSB remove)
3: bit(10..3) (3LSB remove) / R/W / 00
R = Read Only; W = Write; R/W = Read/Write; N = Not exist;
PP_CTRL_REG1 ($0x000008)
Bit / Name / Description / Type / DefaultRegister Description: Provide common and basic control signals for PP process. / 0x00000020
31-15 / RESERVE0 / /
14 / pp_lbus_test_data_gen / If pp_lbus_test_en is set to ‘1’, a rising edge transition on this bit will cause lbus transmitting part on all PP FPGAs to send 8 lbus test words to SL FPGA at the same time. The lbus test data received by SL FPGA is stored in SL in fifos, from where the test data can be read out by ECS to check lbus. / R/W / 0
13 / pp_lbus_test_en / It this bit is set to ‘1’, PP lbus test is enabled on PP FPGA. The normal data stream will be corrupted.
Otherwise, PP lbus transmitting part (on PP FPGA) works in normal mode. / R/W / 0
12 / MCMS_enable / Mean CM subtraction enable, CM subtraction before re-ordering for the velo / R/W / 0
11 / Histogram_enable / The histogram can only be read if this bit is set to ‘1’, it is not updated during the read operation, set back to ‘0’ to allow the processor to update it / R/W / 0
10 / PP_USED / Bit to indicate that this PP-FPGA is used for DAQ, can be used to disable the chip to sent data to the SyncLink / R/W / 1
9 / force_info_disable / Allows to disable the error bank at PP / R/W / 0
8 / force_info_enable / Allows to force the error bank being created / R/W / 0
7 / header_correction_enable / Enables the header correction for the CMS algorithm for Velo and ST / R/W / 0
6-0 / CLUS_DERAN_USE_THR / Threshold for cluster de-randomizer
(in events. VELO has max 128, OPT max 64) / R/W / 0x20
R = Read Only; W = Write; R/W = Read/Write; N = Not exist;
ORX_CTRL REG ($0x00000C)
Bit / Name / Description / Type / DefaultRegister Description: O-Rx control bits, bit error rate test mode / 0x3F003F09
31 / RESERVED2 / 00
30 / ENABLE_ALL_ORX / 1=Enable all orx channels
0=Disable all orx channels / R/W / 0
29- 24 / ORX_LCK_REF / Lock to reference output to TLK set 1 for normal operation / R/W / 0x3F
23- 14 / RESERVED1 / 0000000000
13- 8 / ORX_LINK_DISABLE / One hot encoded disable signal for each optical link 1 = disable, 0 = enable
Set 0 for normal operation / R/W / 111111
7-6 / RESERVE0 / 00
5 / ORX_PRBS_EN345 / Pseudo Random Bit Test Enable signal for Optical card channels: 3, 4, 5.
0 = no pseudo random test
1 = enable pseudo random test / R/W / 0
4 / ORX_LOOP_EN345 / Internal loop-back enable signal for Optical card channels: 3, 4, 5.
0 = disable loop-back, means standard operation.
1 = enable Optical card internal loop-back / R/W / 0
3 / ORX_EN345 / Device Enable signal for Optical card channels: 3, 4, 5.
1 = Enable these 3 optical channels
0 = Puts relative circuit of Optical card in power down mode. / R/W / 1
2 / ORX_PRBS_EN012 / Pseudo Random Bit Test Enable signal for Optical card channels: 0, 1, 2.
0 = no pseudo random test
1 = enable pseudo random test / R/W / 0
1 / ORX_LOOP_EN012 / Internal loop-back enable signal for Optical card channels: 0, 1, 2.
0 = disable loop-back, means standard operation.
1 = enable Optical card internal loop-back / R/W / 0
0 / ORX_EN012 / Device Enable signal for Optical card channels: 0, 1, 2.
1 = Enable these 3 optical channels
0 = Puts relative circuit of Optical card in power down mode. / R/W / 1
R = Read Only; W = Write; R/W = Read/Write; N = Not exist;
PPTEST_REG ($0x000010)
Bit / Name / Description / Type / DefaultRegister Description: To be used for local bus tests / 0x1234ABCD
31..0 / For test use, no functionality / R/W / 1234ABCD
R = Read Only; W = Write; R/W = Read/Write; N = Not exist;
2.2 Common Monitor registers
CONSTANT_REG ($0x001000)
Bit / Name / Description / Type / DefaultRegister Description: Constant informations / Note
31-24 / Reserved / R / \
7-4 / DETECTOR_ID / used to distinguish different synchronizer designs. Use 0x1 for Velo, 0x2 for ST, 0x3 for OT, 0x4 for Cal, 0x5 for
Muon, 0x6 L0MUON, 0x7 for L0DU, 0x8 L0PUS, 0x9 RICH / R / \
3 / RESERVE0 / \
2-0 / CHIPADDR / Hard-wired chip address. / R / \