Spring 2004

Prepared on Feb 12, 2003

DESIGN PROJECT 1: Counter Modules
Due: Wednesday, March 24, 2004 (in class); 100 points (5% of course grade)

Objective:

I. Project Overview

This semester, you will be designing and implementing the datapath and control logic for a digital stopwatch, shown in Figure 1. The stopwatch is to have a five digit 7-segment LCD display and four buttons to control its operation. It can measure the elapsed time in seconds starting from0:00:00 up to 9:59:59 (9 hours, 59 minutes and 59 seconds). It can also be set to a specified time and can count down to 0:00:00. Notice that there are labels for digits and buttons that we will be using for the references through out this description.

The stopwatch has two modes; namely 1) stopwatch mode and 2) timer mode. In a stopwatch mode (the default mode), the stopwatch can be reset to 0:00:00by pressing and releasing the RESET button. When you push theSTART_STOP button once, it will begin counting up and display the elapsed time in a resolution of seconds. A second push of theSTART_STOP button will pause the current clock (time count). The stopwatch continues to count up or pauses with each push of START_STOP button.A lap time can also be shown by pressing (and release) the SETbutton while in stopwatch mode. Going back to stopwatch mode can be done by pressing the SET button again. The difference between pausing the watch and using the lap time is that for the lap time, the stopwatch is still counting while displaying the lap time, even though the time displayed does not change.

When the MODE_INC button is pressed for the first time, the stopwatch will go to thetimer mode where it counts the time backwards. In timer mode, the hour, upper minute (tens) and lowerminute (ones) digits can be selected by pressing the SET button repeatedly. TheMODE_INC button will be used to increment the selected digit, which allows the user to set the stop watch to any desired time in a resolution of minutes. Countingdown starts with the push of theSTART_STOP button. Similar to the stopwatch mode, counting down can be paused or continued with each push of START_STOP button. In timer mode, when the time reaches 0:00:00, the alarm will ring. The watch can be put into a snooze mode by pressing the SETbutton while the alarm is ringing. It will snooze for 5 minutes. At this point, the RESET button needs to be pressed to go back to the default mode (stopwatch mode).Table 1 describes the functionality of digits and push buttons on the stopwatch.Figure 1 shows the stop-watch display from the top level design.

TABLE 1:Function(s) of digits and push buttons

Name / Function(s)
Digits / H / Hour digit
UM / Upper minute (tens) digit
LM / Lower minute (ones) digit
US / Upper second (tens) digit
LS / Lower second (ones) digit
Push buttons / SET / In the stopwatch mode, pressing set displays the lap time. In the timer mode, present set selects a digit (to increment using MODE_INC) and snoozes the alarm when the alarm is ringing.
RESET / Resets all digits to 0, then goes to stopwatch mode
MODE_INC / Switchesbetween stopwatch mode and timer mode. Increments selected digit in thetimer mode
START_STOP / Starts, stops, and resumes counting

Figure 1.Stop-watch Display

Figure 2.Hierarchical structure of stopwatch design

The stopwatch will be designed using hierarchical structures shown in Figure2. The top level design will contain five logic blocks (modules) and some of theses blocks willconsist of smaller sub-blocks. Brief description of each block isgiven below:

  • STOPWATCH: Top level component of the stop watch
  • PBI (Push Button Interface) : Synchronize push button signal with 10Hz clock
  • CSL(ControlState Logic): Sequential State machine for control.
  • COL(Control Output Logic): Decodes CSL output to generate control signal for COUNT_BLK
  • CLK_DIV(Clock Divider): Generates a 1 second clock signal using 10Hz system clock.
  • COUNT_BLK(Counter Block) : 5 digit(H, UM, LM, US, and LS) up/down counter
  • SUL (Sequential Update Logic): Sequential state machine to control the Count Block.
  • MSINC(Mode Selectable increment/decrement ) : increment/decrement 4-bit input by 1and has a mode select(Modulo 6 or Modulo 10)
  • CLAdder_4 : 4-bit Carry LookaheadAdder
  • m6vgandm10vg: (modulo 6 value generator and modulo 10value generator) : Takesina 4-bit BCD input and theup_down signal, andgenerates a 4-bit offset value to be added to the 4-bitBCD input to produce the next value
  • mux21_4 (4-bit 2-to-1 multiplexer): Select between a pair of 4-bit inputsusing a control signal.
  • Lap: To store and display lap value for stopwatch mode
  • Snooze: To store snooze value (5 minutes) for timer mode

For project 1, you will design and verify following five modules:CLAdder_4, m10vg, m6vg,mux21_4 and MSINC.Other modules will be completed in Project 2.

II. Design and Project Report Guidelines

Here are some design and project report guidelines.

  • Use the checklist (last page of this description) as a cover page of your Project 1 report.
  • Wires must be drawn either horizontally or vertically.
  • Never overlap symbols or gates; wires/buses should not cross symbols or gates.
  • Always label symbols.
  • You are to minimize the logic (gate counts) whenever possible.
  • Your report must be in the EXACT same order as appears on the checklist (last page).
  • Make sure you turn in as requested (Trace, List or both). Turn in non-requested part will be penalized.
  • Your report must be page numbered. All schematics, symbols, trace windows, and list output files should be clearly labeled and scaled (zoomed in/out) to show all the contents.
  • Your comments on test cases should clearly demonstrate your understanding of each module’s functions and expected behaviors.
  • Partial credit will be given for non working project, if extensive explanation on describing where it went wrong and the possible solutions are included in the project report (You don’t have to do this if your project is working fine)
  • Hand-written page numbers, test cases, validations and comments are acceptable, but they should be readable.
  • A fancy cover or binding is not required, but use a proper staple or clip to secure all pages.
  • Finally, you are not to delete, modify or remove any of your files after the project has been submitted until you are instructed to do so. We may ask you to demonstrate your project to verify or to clarify your submitted work.

Any reports that do not follow the above design and project report guidelines are subject to a penalty (point deductions). A late project submission carries a hefty 10% late penalty for each 24-hour period, up to 72-hours. No project report will be accepted more than 72 hours after the due date.

CAFE

First, read CAFÉ Documentation in the Course Materials (available from Bob’s copy shop) carefully. Here are some examples. To create an input file to be used for CAFÉ using tableas a function specification (use table as a specification head). You can use any text editors such as vi, emacs, pico, nedit etc to create the input file.

table
2 X Y. ECE 352 Spring: John Doe: UW-ID: xxx-xxx-xxxx
1 Z.
0 0 0
0 1 1
1 0 1
1 1 0.
<process>
e Z.

Figure 3. An Example CAFÉ Input File for XOR Function using truth table.

The Functional Specification, “table”, specifies how we will provide the function specifications. The second line “2 X Y. ECE…” specifies that there are two inputs X and Y. Anything to the right of ‘.’ is considered to be a comment. The third line is specifying there is one output Z. The next four lines contain the values for the truth table. The Process Specificationblock starting with “process,” tells CAFÉ what to do and what to write to its output file.

In order to generate the café output file, you will type “café xor.input xor.output” at the Unix prompt, where xor.input is the name of the input file shown in Figure 3. You can view the result by opening the output file using any text editor.

Note: Pay attention to the period(‘.’) after input line, output line, the end of the table, and the end of the process line(e Z .) . The dots have to be there to run the CAFÉ..

III. Design of Modules

NOTE: Café and force files for the Project 1 can be downloaded fromthe course website.

  1. CLAdder_4: 4-bit Carry Lookahead Adder

TheCLAdder_4module is a 4-bit Carry Lookahead Adder, which adds two 4-bit operands and carry-in to generate a 4-bit sum and carry-out. This CLAdder_4 consists of two different blocks. The first block is a Partial Full Adder (PFA), and the second block is a Carry Lookahead Unit (CLU). If you are not familiar with Carry Lookahead Adder, please refer to p.206-209 of the text book.

1.a. PFA(Partial Full Adder)

The table for PFA is given, and you need to generate the equations using a completed CAFE input file and the following command at the Unix prompt: cafePFA.cafe > PFA.out. Once you get the results, use design architect (da) to build the PFA module. Make sure that you group the terms in the equations whenever possible to minimize the number of gates required for implementation. Designs with an excessive number of gates will be penalized. The PFA.cafe file is provided from the course homepage for your convenience.

TABLE 2:A truth table forPFA.

Inputs / Outputs
A / B / CIN / S / G / P
0 / 0 / 0 / 0 / 0 / 0
0 / 0 / 1 / 1 / 0 / 0
0 / 1 / 0 / 1 / 0 / 1
0 / 1 / 1 / 0 / 0 / 1
1 / 0 / 0 / 1 / 0 / 1
1 / 0 / 1 / 0 / 0 / 1
1 / 1 / 0 / 0 / 1 / 0
1 / 1 / 1 / 1 / 1 / 0

Labels (names) for input/output ports are given below. Note that the labels must be exactly as shown below to use the provided force file. The labels are case sensitive (‘a’ and ‘A’ are different).

  • Inputs: A, B, CIN
  • Outputs: S, G, P

Use the provided force file PFA.force to test your module. Scale your trace window so that it will print out on a reasonable number of pages. A general rule is that your print out must show values of input/output ports and should also have enough space to write comments. Verify and show that your design works correctly with appropriate comments on your trace window printouts. Non-annotated traces will be penalized. You are to submit the following:

  • The schematic of PFA
  • The café output filePFA.outfor PFA
  • Annotated Traces from running the force file PFA.force. Non-annotated traces will be penalized.

Once you have verified the correct functionality of your PFA circuit, generate a symbol for this module.

1.b. CLU_2(2-bit Carry Lookahead Unit)

This is the unit that will make the Carry Lookahead Adder happen. For CLU, refer to

Figure 5-6b in the text book. The CLU in the text book is for a 4-bit adder. In this project, you must modify it to make a Carry Lookahead Unit (CLU) for a 2-bit adder.

Start this part by filling the truth table shown on Table 3. Put it into café form, and run the output. Use the equations(after minimization) and design using da.

Labels (names) for input/output ports are given below. Note that the labels must be exactly as shown below to use the provided force file.

  • Inputs: CIN, P1, P0, G1, G0
  • Outputs:C2, C1, C0

Use the provided force file CLU_2.force to test your module. Non-annotated traces will be penalized. You are to submit the following:

  • The schematic of CLU_2
  • The café output file CLU_2.out for CLU_2
  • Annotated List(Not trace. You don’t have to summit trace for this part) from running the force file CLU_2.force.

Once you verifythe functionality of your CLU_2 circuit, generate a symbol for this module.

TABLE 3:A partially filled truth table forCLU_2.

Inputs / Outputs
CIN / P1 / P0 / G1 / G0 / C2 / C1 / C0
0 / 0 / 0 / 0 / 0
0 / 0 / 0 / 0 / 1
0 / 0 / 0 / 1 / 0
0 / 0 / 0 / 1 / 1
0 / 0 / 1 / 0 / 0
0 / 0 / 1 / 0 / 1
0 / 0 / 1 / 1 / 0
0 / 0 / 1 / 1 / 1
0 / 1 / 0 / 0 / 0
0 / 1 / 0 / 0 / 1
:
1 / 1 / 1 / 0 / 1
1 / 1 / 1 / 1 / 0
1 / 1 / 1 / 1 / 1

1.c. CLAdder_4 (4-bit Carry Lookahead Adder)

Using PFA and CLU_2 units, build the 4-bit Carry Lookahead Adder shown on figure 4.

Side note: The performance of a 4-bit adder will be better with the 4-bit CLU (shown in

Figure 5-6b of the text book. However, for this project, use the 2-bit unit described above. The purpose of using CLU_2 is to illustrate the concept of hierarchy. Such a hierarchy can be used, for example, to build a 16-bit adder using the 4-bit adder in the text.

Figure 4. Hierarchy structure of CLAdder_4.

Labels (names) for input/output ports are given below. Note that the labels must be exactly as shown below to use the provided force file.

  • Inputs: A3, A2, A1, A0, B3, B2, B1 ,B0 CIN
  • Outputs:S3, S2, S1, S0, COUT

Use the provided force file CLAdder_4.force to test your module. Non-annotated traces will be penalized. You are to submit the following:

  • The schematic of CLAdder_4
  • Annotated List from running the force file CLAdder_4.force
  • Annotated Traces from running the force file CLAdder_4.force.Non-annotated traces will be penalized.Make sure it’s readable (you might need to do some zooming).

Once you verifythe functionality of your CLAdder_4 circuit, generate a symbol for this module.

  1. m10vg: modulo 10value generator

For clocks or stopwatches valid digits for the Upper Minute (UM) and Upper Second (US) (tens place) are 0, 1, 2, 3, 4 and 5. Whereas 0, 1, 2, 3, 4, 5, 6, 7, 8 and 9are valid digits for the Hour (H), Lower Minute (LM), and Lower Second (LS). For example, 0:59:59 is within a valid time range, but 0:69:87 is not within a valid time range. For each digit of stopwatch, we will compute the value of the next digit by adding a 4-bit 2’s complement offset, generated by either m6vgor m10vg module. The m10vgmodulewill be used to generate a 4-bit offset to be added for the H, LM, and LS digits. It will take the value of the current digit as 4-bit BCD and two control signals (up and dn) as inputs to generate a 4-bit offset (m3, m2, m1andm0), carry-out (co) and borrow-out (bo).

Since you are implementing an up/down counter, you need to add +1(=0001b) when up=1 and add -1(=1111b) when dn=1 to the present input value in most cases. However, there are three special cases that you need to consider.The first case is when the current input is 9(=1001b) and we are counting up (up=1 and dn=0), m10vg should generate 7(=0111b) so that the result after the addition is 0. In this case, co should be 1 to indicate there is a carry to a higher digit. Similarly, when current input is 0 (=0000b) and we are counting down, we need to add 9(=1001b) and boshould be 1 to indicate a borrow is needed from the adjacent digit. Finally whenup and dn are both logic 0, the offset value to add is 0(=0000b).

Assume that both up and dn signals cannot be both 1. A partially completed truth table for this module is given in Table 3, where ‘-‘represents a don’t care. A partially completed CAFE input file m10vg.cafe is provided for your convenience. Using Table 3, complete the CAFE input file, m10vg.cafe, then generate a CAFE output file by typing in the following command at the Unix prompt: cafe m10vg.cafe > m10vg.out

Once you get the results, use da to build the m10vg module. Make sure that you group the terms in the equations whenever possible to minimize the number of gates required for implementation. Designs with an excessive number of gates will be penalized.

Labels (names) for input/output ports are given below. Note that the labels must be exactly as shown below to use the provided force file.

  • Inputs : i3, i2, i1, i0(4-bit present input), up and dncontrolsignals
  • Outputs: m3, m2, m1 and m0(a 4-bit offset value to be added to the current inputs), coandbo for carry-out and borrow-out, respectively.

TABLE 3:A partially filled truth table form10vg.

Inputs / Outputs
up / dn / i3 / i2 / i1 / i0 / m3 / m2 / m1 / m0 / co / bo
0 / 0 / - / - / - / - / 0 / 0 / 0 / 0 / 0 / 0
1 / 1 / - / - / - / - / - / - / - / - / - / -
0 / 1 / 0 / 0 / 0 / 0 / 1 / 0 / 0 / 1 / 0 / 1
0 / 1 / 0 / 0 / 0 / 1 / 1 / 1 / 1 / 1 / 0 / 0
0 / 1 / 0 / 0 / 1 / 0 / 1 / 1 / 1 / 1 / 0 / 0
0 / 1 / 0 / 0 / 1 / 1 / 1 / 1 / 1 / 1 / 0 / 0
0 / 1 / 0 / 1 / 0 / 0 / 1 / 1 / 1 / 1 / 0 / 0
0 / 1 / 0 / 1 / 0 / 1 / 1 / 1 / 1 / 1 / 0 / 0
0 / 1 / 0 / 1 / 1 / 0 / 1 / 1 / 1 / 1 / 0 / 0
0 / 1 / 0 / 1 / 1 / 1 / 1 / 1 / 1 / 1 / 0 / 0
0 / 1 / 1 / 0 / 0 / 0 / 1 / 1 / 1 / 1 / 0 / 0
0 / 1 / 1 / 0 / 0 / 1 / 1 / 1 / 1 / 1 / 0 / 0
0 / 1 / 1 / 0 / 1 / - / - / - / - / - / - / -
0 / 1 / 1 / 1 / - / - / - / - / - / - / - / -
1 / 0 / 0 / 0 / 0 / 0
1 / 0 / 0 / 0 / 0 / 1
1 / 0 / 0 / 0 / 1 / 0
1 / 0 / 0 / 0 / 1 / 1
1 / 0 / 0 / 1 / 0 / 0
1 / 0 / 0 / 1 / 0 / 1
1 / 0 / 0 / 1 / 1 / 0
1 / 0 / 0 / 1 / 1 / 1
1 / 0 / 1 / 0 / 0 / 0
1 / 0 / 1 / 0 / 0 / 1
1 / 0 / 1 / 0 / 1 / - / - / - / - / - / - / -
1 / 0 / 1 / 1 / - / - / - / - / - / - / - / -

Use the provided force file m10vg.force to test your implementation. Verify and show that your circuit works correctly by commenting on a list window printout. You are to submit the following:

  • The completed café input file m10vg.cafeand output files m10vg.outfor m10vg
  • The schematic of m10vg
  • Annotated List from running the force file m10vg.force.

Once you verifytheimplementation, generate a symbol and save it for later use.

  1. m6vg:modulo 6add value generator

The m6vgis similar to m10vg, except that it will be used to compute offsets for Upper Minute (UM) and UpperSecond(US) digit.The legal input values of m6vgare 0, 1, 2, 3, 4, and 5. Notice that you do not need the most significant bit i3.

The basic function of m6vgis similar to that of m10vg. However, the offsets for two special cases are different. The first case is when the current input is 5 (=0101b) and counting up (up = 1), m6vg should generate an offsetso that you get 0 when 5 is added to the offset. The output co should be1 to indicate that there is a carry. Similarly, when the current input is 0 (=0000b) and counting down (dn = 1), we need to generate a different offset and set bo to 1to indicate a borrow is needed from the higher digit. Assume that both up and dn signal cannot simultaneouslybe 1. A partially filled truth table for m6vgis given in Table 4. Complete the following table and create a CAFE input file to find a minimum implementation for m6vg. Make sure that you use don’t cares wherever possible to minimize the implementation cost. Once you complete the truth table, create a CAFE input file, m6vg.cafe. Generate the corresponding CAFÉ output file m6vg.out. Once you get the equations, use da to implement the circuit.