Multi-Rate Filters
ECE Capstone Design Project, Spring ‘14
Students: Mitch Gollub, Jay Nadkarni, Digant Patel, Sheldon Wong
Advisor: Dr. Spasojevic
Abstract
Introduction
Digital filters are a critical part of the growing field of technology. Devices and machines commonly use signals to transfer information which must be filtered or manipulated in order for other devices to interact .The goal of this project is to explore a set of reliable multirate filter designs and construction methods for specific hardware applications. One specific difficulty in filter design is the climbing computational load of a high sampling rate system. The greater the number of samples, the greater the number of computations a system must perform. These multirate filters are commonly implemented as a bank of FIR(Finite Impulse Response) filters. One of the main topics of optimization investigated was the benefits of decimating an input signal to decrease computational load.
Design
Before moving into the hardware implementation, the first objective was working in MATLAB to construct a filter bank model. There are five essential steps including: determining filter specifications, filter coefficient calculation, structure design, simulation using Simulink, and migration to a hardware implementation. MATLAB offers various filter toolboxes that aid in the design of these FIR filters (fdatool). Using Simulink, which is an extension of MATLAB, it was possible to test block designs and observe the input/output signals of the design. MATLAB was also critical in determining the MACs(Multiply and Accumulate Computations) which is used to illustrate the performance benefits of different filter designs. The most efficient designs were selected to be modified into VHDL code so that it can be run on an FPGA board. LabView is utilized to sync the specified designs to the myRIO FPGA for filtering on the hardware.
Conclusion
Progressively the team navigated through filter hierarchy and along the way learned about the many different aspects of creating an efficient filter from design to hardware implementation. Challenges steadily arose, but provided for an excellent learning journey. Future project work includes experimenting with distributed processing/pipelining features that are inclusive on the FPGA’s we worked with. While the experiments produced valuable filtering results, the team understands there are many more optimizations that can be made to further the project goals.