ECE 477 Digital Systems Senior Design Project Spring 2006
Homework 6: Printed Circuit Board Layout Design
Due: Friday, February 24, at NOON
Team Code Name: The Soviet Challenge______Group No. _6__
Team Member Completing This Homework: Allan Patterson______
Evaluation:
Component/Criterion / Score / Multiplier / PointsIntroduction & Layout Considerations / 0 1 2 3 4 5 6 7 8 9 10 / X 3
Documentation for PCB Layout Design / 0 1 2 3 4 5 6 7 8 9 10 / X 5
List of References / 0 1 2 3 4 5 6 7 8 9 10 / X 1
Technical Writing Style / 0 1 2 3 4 5 6 7 8 9 10 / X 1
TOTAL
Comments:
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1.0 Introduction
The Soviet Challenge is a portable, hand-held, wireless capable device designed to run the client software of TetriNET, a multiplayer, online Tetris clone. The major features of the device include a power circuit for regulating the input battery voltage, as well as recharging the battery, a main microcontroller for implementing the TetriNET software, as well as integrating all the other components, and an RS-232 interface to an LCD display.
Due to the portable nature of the device, size constraints are one of the foremost concerns in PCB layout. Also, the device uses a wireless CompactFlash network card to access an internet connection, which presents communications issues internally and externally. The input buttons for the device connect to the board from a distance via headers, and hence need a secure connection onto the board. Finally, the device must transform the input voltage from the +7.4V lithium-ion battery to a usable form for the +3.3V devices, and the AC input must be regulated to +8.4V to recharge the battery.
2.0 PCB Layout Design Considerations
The Soviet Challenge, being a handheld device, required some careful considerations in terms of PCB layout. The device has several major sections to consider for the PCB layout. These sections are as follows:
1) Power Circuit – This circuit must regulate battery voltage from +7.4V to +3.3V to all onboard devices, as well as regulate a standard AC wall input to +8.4V DC to charge the battery. Additionally, has to provide an analog battery level to the microcontroller.
2) Communication Circuit – Communicates from the microcontroller to the ezLCD-001 display adapter via RS232.
3) Reprogramming Circuit – Headers drawn from the microcontroller for in-circuit debugging and microcontroller reprogramming.
4) LCD Circuit – The ezLCD-001 interfaces via a pair of spaced headers which occupy the left and right portions of the center of the PCB, leading to necessary considerations for routing signals to and from the nearby microcontroller.
5) Wireless CompactFlash Circuit – Requires a 50 pin inline connector, of which, 26 must be run straight to the microcontroller.
6) Button Circuit – A 12 pin header, along with a PLD to reduce the large number of input buttons.
7) Microcontroller Circuit – A 64 pin Atmega2561, requires several connections to +3.3V, as well as traces to be run in all four directions, as almost all the pins are being used.
The most crucial constraint on our design is that the entire PCB must fit inside the 5.1” wide by 3.4” tall enclosure of our selected case for the device. Also, the final PCB will be placed directly on top of the rechargeable battery inside of the case, so any parts that stick out considerably or have special routing requirements off of the PCB should be placed on the top layer of the PCB if at all possible. In the design, we successfully adhered to this, having only the microcontroller placed on the bottom of the board, as will be discussed later.
Due to the design and layout of the device, several components had very obvious locations for placement on the PCB. The custom CompactFlash connector for the wireless card had to be placed near one of the four edges of the PCB, and as a team we agreed that the top edge made the most sense – the way a user would hold the device, this configuration is the most aesthetically balanced, as well as functional, as the wireless card will be facing outward from the user, giving it the most interference-free path to a wireless access point possible. In addition to this, the ezLCD-001 component mounts onto a PCB via a set of two headers, one that is two by six pins, and one that is two by thirteen pins. The most logical place for the screen to be located is directly in the middle of the device. Per these facts and the mechanical drawing [1] provided by EarthLCD (and confirmed by us in lab), the headers were spaced a total of 2.8 inches apart on the board, measured from the outer edge of each header. Due to the pin layout of the our CompactFlash header as a single row surface mount pad per [2] (Page 37, Figure 19), and a desire to use entire microcontroller ports to transmit data such as the data and address buses to simplify the future software requirements, the easiest way to place the CompactFlash header and the microcontroller is to have one of the parts on the opposite layer of the board from the other. Because of the large connection footprint of the CompactFlash wireless card, and the consideration of the battery sitting directly below the PCB, the best solution was to place the microcontroller on the bottom layer of the board, and to keep the CompactFlash header on the top.
As it turned out, this placement of the microcontroller made tracing the signals out to all the various connection points on the board somewhat easier to accomplish than our initial attempt at layout, allowing us to not have to resort to nearly the tight bunching of signals, nor overuse of vias, as our initial, and ultimately unsuccessful layout attempt. Also, as the microcontroller connects to every other circuit on the board, it was placed in the direct middle of the PCB. The layout of the power circuit was then implemented on the left side of the board, as this was the location of the smaller ezLCD-001 header, and thus had the most room for all the surface mount resistors and capacitors needed for our power logic. The large amount of room available was particularly helpful for laying out the battery charging logic, as all of these components use a large amount of current relative to the rest of the device, and as such larger traces are required.
In terms of the remaining components, the rule of thumb for layout was to keep the most important and time sensitive components closer to the microcontroller. For example, the crystal for setting the clock rate of the microcontroller, and its required surface-mount capacitors per [3] are placed close to the microcontroller, versus the user input buttons on the device, which are much less time-sensitive, and consequently wired on one of the far edges of the microcontroller. In addition, the reprogramming circuit, a feature not actually needed for the final operation of the device, is placed far to one end of the board, so as not to waste short traces from the microcontroller – in addition, this was one of the last components to be routed, as it was far less important for it to have direct traces or no vias present than other components.
In terms of trace sizing, the power and ground traces, in particular, need to be large in order to lower the effective resistance of the traces, keeping the voltage levels of power and ground as constant as possible over all devices, as well as allowing larger amounts of current to travel through the traces. The ground trace was placed on the bottom layer of the board as much as possible, while power was placed on the top layer of the board – in addition, decoupling capacitors were placed on the inputs to all major components on the PCB in order to ease the burden on the power lines and prevent glitches from occurring in the power system due to instantaneous current requirements as specified in [4]. In order to expedite the layout of the rest of the board, power and ground were fully routed to all blocks before any other signals were attempted, and several components were adjusted in spacing to account for any issues encountered with running wide traces to these components. For the remainder of the traces, widths of 12 mils were selected, lying on the larger end of the minimal size recommended by the course staff in [5], in order to route signals from various logical blocks throughout the circuit.
3.0 Summary
The Soviet Challenge provides an interesting challenge in PCB layout as a result of its small size requirements, a necessity for portability. In order to overcome these problems, intelligent initial layout of components, as well as heavy usage of the available area on the board allows us to overcome this problem and successfully layout and route all of the necessary components.
List of References
“ezLCD-001 Mechanical Drawing,”, [Online Document] 2005 December,
Available HTTP: http://www.ezlcd.com/files/ezLCD-001_dwg.pdf
“CF+ and CompactFlash Specification Revision 3.0”, [Online Document] 2004 December
Available HTTP: http://shay.ecn.purdue.edu/~477grp6/joe/pdf/compactflash.pdf
“HC49-US SMD low profile crystal”, [online document] 2002 November [February 24,
2006]
Available HTTP: http://www.qct.nl/crystals/HC49-US-SMD/HC49-US-SMD.html
“System Design and Layout Techniques for Noise Reduction in MCU-Based Systems”,
Motorola Semiconductor Application note AN1259/D [Online Document] 1995.
Available HTTP: http://shay.ecn.purdue.edu/~dsml/ece477/Homework/Spr2006/AN1259.pdf
“Digital Systems Senior Design Project Module 2 –PCB Layout Basics”, [Online
Document] 2006 January.
Available HTTP: http://shay.ecn.purdue.edu/~dsml/ece477/Notes/PDF/4-Mod2.pdf
Appendix A: Routing Statistics Report
*********************************
* STATISTICS REPORT *
* N:\PCB\TETRINET\TETRINET.MAX *
* Fri Feb 24 00:35:14 2006 *
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STATISTIC ENABLED TOTAL
------
Board Area 16.8 16.8
Equivalent IC's 21.2 21.2
Sq. inches per IC 0.79 0.79
# of pins 318 318
Layers 3 28
Design Rule Errors 0 0
Time Used 21:17 21:17
% Placed 100.00% 100.00%
Placed 51 51
Off board 0 0
Unplaced 0 0
Clustered 0 0
Routed 197 197
% Routed 100.00% 100.00%
Unrouted 0 0
% Unrouted 0.00% 0.00%
Partials 0 0
% Partials 0.00% 0.00%
Vias 148 148
Test Points 0 0
Vias per Conn 0.75 0.75
Segments 1590 1590
Connections 197 197
Nets 86 86
Components 51 51
Footprints 124 124
Padstacks 54 54
Obstacles 421 421
Theoretical Dist 188.8 188.8
Routed Dist 213.5 213.5
Unrouted Dist 1.9 1.9
-5-