i. CODE:
module top_fpga (
input clk1,
//input clk2,
input data,
input D1,
input D2,
input D3,
input D11,
input D22,
input D33,
output OUT);
//======zzz=====
BUFG BUFG_CLK1(.I(clk1),.O(clk1_AFTERBUFG));
reg QA0;
always @(posedge clk1_AFTERBUFG)
begin
QA0<=D1&D11;
end
reg QA1;
wire clk2_AFTERBUFG=clk1_AFTERBUFG&D11&D22&D33;
//======zzz=====
//======zzz=====
reg QAB;
always @(posedge clk2_AFTERBUFG)
begin
QAB<=QA0;
end
//======zzz=====
//======zzz=====
assign OUT=QA0 & QAB ;
endmodule
ii. SDC:
define_clock {{p:clk1}} -name {xxx} -period 10 -clockgroup default_clkgroup_11
define_clock {n:clk2_AFTERBUFG} -name {yyy} -period 20 -clockgroup default_clkgroup_12
iii. UCF:
NET "clk1" TNM_NET = "clk1";
TIMESPEC "TS_clk1" = PERIOD "clk1" 10.000 ns HIGH 50.00%;
NET "clk2_AFTERBUFG" TNM_NET = "clk2_AFTERBUFG";
TIMESPEC "TS_clk2_AFTERBUFG" = PERIOD "clk2_AFTERBUFG" 20.000 ns HIGH 50.00%;
iv. PCF:
SCHEMATIC START;
TIMEGRP clk1 = BEL "QA0" BEL "QAB";
TIMEGRP clk2_AFTERBUFG = BEL "QAB";
TS_clk1 = PERIOD TIMEGRP "clk1" 10 ns HIGH 50%;
TS_clk2_AFTERBUFG = PERIOD TIMEGRP "clk2_AFTERBUFG" TS_clk1 * 2 HIGH 50%;
SCHEMATIC END;
v. TIMING ANALYZER:
======
Timing constraint: TS_clk1 = PERIOD TIMEGRP "clk1" 10 ns HIGH 50%;
1 item analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors)
Minimum period is 3.859ns.
------
Slack (setup path): 6.141ns (requirement - (data path - clock path skew + uncertainty))
Source: QA0 (FF)
Destination: QAB (FF)
Requirement: 10.000ns
Data Path Delay: 2.792ns (Levels of Logic = 0)
Clock Path Skew: -1.067ns
Source Clock: clk1_AFTERBUFG rising at 0.000ns
Destination Clock: clk2_AFTERBUFG rising at 10.000ns
Clock Uncertainty: 0.000ns
Data Path: QA0 to QAB
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------
SLICE_X65Y174.YQ Tcko 0.258 QA0
QA0
SLICE_X81Y226.BY net (fanout=2) 2.313 QA0
SLICE_X81Y226.CLK Tdick 0.221 QAB
QAB
------
Total 2.792ns (0.479ns logic, 2.313ns route)
(17.2% logic, 82.8% route)
Hold Paths: TS_clk1 = PERIOD TIMEGRP "clk1" 10 ns HIGH 50%;
------
Slack (hold path): 0.202ns (requirement - (clock path skew + uncertainty - data path))
Source: QA0 (FF)
Destination: QAB (FF)
Requirement: 0.000ns
Data Path Delay: 2.313ns (Levels of Logic = 0)
Clock Path Skew: 2.111ns
Source Clock: clk1_AFTERBUFG rising at 10.000ns
Destination Clock: clk2_AFTERBUFG rising at 10.000ns
Clock Uncertainty: 0.000ns
Data Path: QA0 to QAB
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------
SLICE_X65Y174.YQ Tcko 0.237 QA0
QA0
SLICE_X81Y226.BY net (fanout=2) 2.128 QA0
SLICE_X81Y226.CLK Tckdi (-Th) 0.052 QAB
QAB
------
Total 2.313ns (0.185ns logic, 2.128ns route)
(8.0% logic, 92.0% route)
vi. CACULATE THE CLOCK SKEW:
l CLK1èQAB
SETUP PATH:
------
Delay (setup path): 6.341ns (data path)
Source: clk1 (PAD)
Destination: QAB (FF)
Data Path Delay: 6.341ns (Levels of Logic = 3)
Constraint Improvement Wizard
Data Path: clk1 to QAB
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------
AJ17.I Tiopi 0.736 clk1
clk1
clk1_ibuf
BUFGCTRL_X0Y0.I0 net (fanout=1) 0.793 clk1_c
BUFGCTRL_X0Y0.O Tbgcko_O 0.700 BUFG_CLK1
BUFG_CLK1
SLICE_X65Y174.F1 net (fanout=2) 2.339 clk1_AFTERBUFG
SLICE_X65Y174.X Tilo 0.146 QA0
clk2_AFTERBUFG
SLICE_X81Y226.CLK net (fanout=1) 1.627 clk2_AFTERBUFG
------
Total 6.341ns (1.582ns logic, 4.759ns route)
(24.9% logic, 75.1% route)
HOLD PATH:
------
------
Delay (hold path): 5.721ns (data path)
Source: clk1 (PAD)
Destination: QAB (FF)
Data Path Delay: 5.721ns (Levels of Logic = 3)
Constraint Improvement Wizard
Data Path: clk1 to QAB
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------
AJ17.I Tiopi 0.612 clk1
clk1
clk1_ibuf
BUFGCTRL_X0Y0.I0 net (fanout=1) 0.729 clk1_c
BUFGCTRL_X0Y0.O Tbgcko_O 0.644 BUFG_CLK1
BUFG_CLK1
SLICE_X65Y174.F1 net (fanout=2) 2.105 clk1_AFTERBUFG
SLICE_X65Y174.X Tilo 0.134 QA0
clk2_AFTERBUFG
SLICE_X81Y226.CLK net (fanout=1) 1.497 clk2_AFTERBUFG
------
Total 5.721ns (1.390ns logic, 4.331ns route)
(24.3% logic, 75.7% route)
l CLK1èQA0
SETUP PATH:
------
Delay (setup path): 4.230ns (data path)
Source: clk1 (PAD)
Destination: QA0 (FF)
Data Path Delay: 4.230ns (Levels of Logic = 2)
Constraint Improvement Wizard
Data Path: clk1 to QA0
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------
AJ17.I Tiopi 0.736 clk1
clk1
clk1_ibuf
BUFGCTRL_X0Y0.I0 net (fanout=1) 0.793 clk1_c
BUFGCTRL_X0Y0.O Tbgcko_O 0.700 BUFG_CLK1
BUFG_CLK1
SLICE_X65Y174.CLK net (fanout=2) 2.001 clk1_AFTERBUFG
------
Total 4.230ns (1.436ns logic, 2.794ns route)
(33.9% logic, 66.1% route)
------
HOLD PATH:
Hold Paths: PATH PATHFILTERS = FROM TIMEGRP "SOURCES" TO TIMEGRP "DESTINATIONS"
------
Delay (hold path): 3.786ns (data path)
Source: clk1 (PAD)
Destination: QA0 (FF)
Data Path Delay: 3.786ns (Levels of Logic = 2)
Constraint Improvement Wizard
Data Path: clk1 to QA0
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------
AJ17.I Tiopi 0.612 clk1
clk1
clk1_ibuf
BUFGCTRL_X0Y0.I0 net (fanout=1) 0.729 clk1_c
BUFGCTRL_X0Y0.O Tbgcko_O 0.644 BUFG_CLK1
BUFG_CLK1
SLICE_X65Y174.CLK net (fanout=2) 1.801 clk1_AFTERBUFG
------
Total 3.786ns (1.256ns logic, 2.530ns route)
(33.2% logic, 66.8% route)
可见：
SETUP PATH / HOLD PATHClk1èQAB / 6.341 / 5.721
Clk1èQA0 / 4.230 / 3.786
CLOCK SKEW(caculated by me) / 6.341-4.230=2.111 / 5.721-3.786=1.845
CLOCK SKEW(from twr report / -1.067ns(error) / 2.111ns
my question is that why the clock skew for the setup path and the hold path are different
between the CLOCK SKEW(caculated by me) and CLOCK SKEW(from twr report)?