ASTR-426/526 Quiz 1: CCD Readout Techniques

Here is an image from RIT showing the nomenclature for CCD readout. The normal one-pixel readout is that with the exposure complete and the shutter closed, the parallel registers undergo one clock sequence (three phase, two phase, … device specific), which deposits charge from the first row into the serial register. The serial clock sequence is then executed n times (n is the number of pixels in the row) and as each pixel is presented to the output amplifier, the signal is read using the double-correlated readout technique usually, amplified, and then presented to an analog-to-digital converter (ADC, not shown) where the signal is digitized and accepted by the control computer as the first digitized pixel of the array. After all n serial pixels are read additional “empty” pixel may continue to be read from the serial register to obtain overscan pixels that measure the bias value for that row.

At the end of the overscan (if any), the parallel clock cycle is again executed to put the second row into the serial register, and it (plus its overscan) are amplified, digitized and stored in computer memory. This procedure is repeated until all m rows are read out. This image is now in computer memory and processing can begin, the image can be viewed, or it can just be stored and the next integration can be started.

The quiz question asked about 2 x 2 binning.

The basic readout scheme is the same, but charge is summed in the serial register prior to being amplified and digitized. This happens in only one sequence:

  1. One row is read into the serial register.
  2. A second row is read into the serial register (resulting in two rows of signal electrons now “summed” into one serial register).
  3. Executing the serial register, the first two pixels are clocked onto the amplifier input.
  4. Note that charge from four pixels (2 x 2 binning) is now present at the input to the output amplifier. Shifting charge without reading it is essentially noiseless – no “switches” have been activated to this point.
  5. This charge is now amplified (sensed – which involves closing switches to sense current, as in the double correlated sample technique). It is the sensing and amplification which adds read-out noise to the signal. We have just read four pixels, but only injected readout noise once.
  6. The major reason for on-chip binning is to increase the signal-to-noise at the expense of angular or spectral resolution.

Note that this last statement is not always true! Imagine you have put a low resolution spectrum on the CCD such that dispersion is along columns. That is, the spectrum might lie between columns 100 and 200. Now (if scientifically justified, necessary or convenient), we can make a parallel shift, putting the first image row into the serial shift register. Now we can rapidly read the first 99 pixels from the serial register, and not digitize them at all! We can simply close the amplifier switch while those 99 pixels are reading to the amplifier, and their charge (electrons) are simply shunted to the substrate – we essentially “empty” them. Starting with pixel 100 we now read the serial register normally until we’re read pixel 200. Then we revert to “dumping” the remainder of the serial register to ground. After the last pixel is read we can assert the vertical clock sequence, put the next row into the serial register and repeat the selective, rapid read sequence. There are a large number of shift sequences that can be usefully employed in astronomy!

The major reason for on-chip binning is noise reduction. It is also used to minimize the number of pixels stored in computer memory (though this is less of an issue these days).

The general equation for signal-to-noise (S/N) associated with detector readout is:

Where S is the background-subtracted detected signal, B is the background signal, r is the readout noise per pixel, and n is the number of pixels summed to derive S and B. Binning simply minimizes n, thus increasing the S/N. And this is the primary reason for on-chip binning – minimizing the contribution to the noise of a measurement, especially when the signal and background levels are low and the readout noise is a significant limitation to the S/N.

Because parallel and serial shifting are essentially noiseless processes (readout noise is only injected by the output amplifier), many shift sequences can generate high signal, low noise data by using a bit of creativity. Can you think of some unique applications for innovative shift sequences and on-chip binning?