University of Saskatchewan

EE800: Circuit Elements in Digital Computations, Spring 2010

Instructor: Seok-Bum Ko

Office: ENGR 3B39, 966-5456

Email:

Class web page: www.engr.usask.ca/classes/EE/800

Time and Location: 1PM – 2:20 PM Tue 1C70, 10AM – 11:20AM Fri 2C90

Prerequisite: EE232 and EE331, or equivalent.

Recommended Text: Computer Architecture: A Quantitative Approach (3rd Edition), J. Hennessy and D. Patterson, Morgan Kaufmann Publishers, 2003

Course Objective:

The goal of this course is to impart a deep understanding of high-performance computer system architecture. The emphasis is on arithmetic logic unit, cache and memory, input/output systems, interconnection networks, and multiprocessors. Logic synthesis will be covered.

Grading:

Final exam: 40 %

Literature review (technical papers related to lectures): 20 %

Term Projects: 40 %

TEMPORARY Course Outline:

Review

Logic Synthesis

ALU

FXP/FPU

Decimal Arithmetic Unit

Cache/Memory

Wk / Date / Topic / ETC
1 / 1/8 / Planning meeting at 3B39
2 / 1/12, 15* / Review (lecture 1) and PD (project discussion) / Spectrum
3 / 1/19, 22 / Logic Synthesis (lecture 2) and PD
4 / 1/26, 29 / Literature review 2
5 / 2/2, 5 / ALU (lecture 3) and PD
6 / 2/9, 12 / Literature review 3
7 / 2/16*, 19* / Mid-term Break
8 / 2/23, 26 / FXP/FPU (lecture 4) and PD
9 / 3/2, 5 / Literature review 4
10 / 3/9, 12 / Decimal Arithmetic Unit (lecture 5) and PD
11 / 3/16, 19 / Literature review 5 and PD
12 / 3/23, 26 / Cache/memory/Multiprocessors (lecture 6) and PD
13 / 3/30, 4/2* / Review / Good Friday
14 / 4/6, 8 / Final Presentation
?? / Final Report
?? / Final Exam

*: Acceptable articles (2007-10 for Literature Review): IEEE Tr. on Computers/VLIS Sytems/Circuits and Systems I and II/Parallel and Distributed Computing, FPGA, FCCM , FPL, DAC, ISCAS