Faculty of Information Engineering & Technology Eng. Salma Hesham

Faculty of Information Engineering & Technology Eng. Salma Hesham

Electrical & Electronics Department Dr. M. Abd El Ghany

Course: Microelectronics Lab ELCT605

Spring 2015

Digital Lab Report 4

Modeling of Sequential Circuits using vhdl

Name / ID / Lab Group

Modeling of Sequential Circuits

Using VHDL

§ Lab Task: (Individual Submission)

I. 4-bit Right Shift Register

II. 4-bit Universal Shift Register

§ Lab Task:

I. 4-bit Right Shift Register

a. Which of the following architectures describes the 4-bit right shift register shown in Fig. 1?

b. Modify architecture #1 or architecture #2 to implement the 4-bit right shift register without changing the order of equation assignment.

§ Lab Task:

II. 4-bit Universal Shift Register

1. Tabulate the function of the 4-bit universal shift register based on the provided block diagram in Fig. 1

S1 / S0 / Q3 / Q2 / Q1 / Q0 / Function
0 / 0
0 / 1
1 / 0
1 / 1

2. Multiplexer 4-to-1

A. Create a new source of type VHDL module named “Mux4x1”. Model the 1-bit multiplexer using concurrent when-else or with-select statement.

B. Create a new source of type VHDL module named “Universal_Shift”. Model the function of the Universal Shift register using mixed architectural modeling: Behavioral + Structural as shown in Fig.3.

C. Create a new source of type VHDL Testbench to test the Universal Shift Register using the input test cases provided by Fig. 5.

D. Perform a behavioral simulation to check the output according to the provided test cases.

E. Synthesize the Code in part (B) to get the RTL schematic, the resources usage and the maximum operating frequency of the design.

F. In terms of the FPGA hardware usage, is the following code more efficient than the code in part (B)? Why?

Synthesize the Code in part (F) by downloading and adding all the VHDL sources needed from the eee.guc.edu.eg website. Compare the results with the results in part (E)