Head: Max's Chips and Dips: a Fabulous Flurry of Activity

@head: Max's Chips and Dips: A Fabulous Flurry of Activity

@deck: There has recently been a fabulous flurry of activity in the chip design community, such as the red-hot announcements from Clairvoyante, Novelics, Optimal, Tensilica, and Certess.

@text: I don't know if it's just the fact that summer is almost upon us (next week is the "Second Third of Spring" and the "Summer Solstice" follows just four weeks later – you can check out the <a href="http://www.glib.com/season_dates.html" target="_new">Dates and Times of the Seasons</a> site for more details), but there has recently been a fabulous flurry of activity and announcements in the chip design community.

Clairvoyante

Let's start with the chaps and chappesses at <a href="http://www.clairvoyante.com" target="_new"Clairvoyante</a>, because I have a "soft spot" for their technology. As you may recall, most of the liquid crystal displays (LCDs) used on handheld electronic equipment have each of their pixels formed from RGB (red, green, and blue) sub-pixels.

By comparison, the folks at Clairvoyante have developed a novel technology in which each pixel is formed from RGBW (red, green, blue, and white) sub-pixels. The result is a display that consumes half the power of standard displays while providing the same brightness, or it can provide twice the brightness while consuming the same amount of power. (If you are interested in learning more, check out the <a href="http://www.diycalculator.com/sp-console.shtml#A12b" target="_new"An Alternative Sub-Pixel Technology</a> topic in my <a href="http://www.diycalculator.com/sp-console.shtml" target="_new"Origin and Evolution of Computer Displays</a> paper.)

Well, hot off the press is the news that Korean fabless chip manufacturer <a href="http://www.tomatolsi.com/index.html" target="_new"Tomato LSI</a> is going to produce the world's first commercially available three-chip RGBW driver for amorphous silicon TFT widescreen VGA display panels up to 5-inches diagonal. This is targeted at 3G mobile display designs where a widescreen version is desirable – such as mobile video players, ultra-portable PCs, global positioning satellite devices, and next-generation mobile phones – to reduce or eliminate the need for horizontal scrolling, thereby greatly enriching the user experience.

Novelics

Next on my list of "cool stuff" is the latest generation of embedded memory technology and associated design tools from <a href="http://www.novelics.com" target="_new"Novelics</a>. There are so many dimensions to this that it's difficult to know where to start. First, they have a "memory compiler" called MemQuest that allows one to specify the exact width and depth of the memory block you require. Also, in the case of appropriate memory types such as SRAM, you can request that the memory be split into a number of sub-blocks, each of which can be individually powered-down (put to sleep) and powered up as required.

But the really cool thing is that you can select the exact type of memory you require, such as their coolSRAM-1T (one transistor), coolSRAM-6T (six transistor), coolOTP (one-time programmable), coolREG (register file), coolROM (read-only memory), and coolCACHE (cache memory for processor cores). The reason for the "cool" portion of these monikers is that these memories are claimed to use half the power of other typical solutions while – at the same time – occupying half the area and providing twice the performance.

But wait, there's more. MemQuest generates all of the files you require throughout the design process. In the case of your initial area, power, and performance tradeoffs, you are presented with the various alternatives in the form of a PDF file. Next, you are presented with .lib, .lef, .v, and .mbist files for use in the design of your SoC, and also with GDSII and .cir files for the downstream implementation and manufacturing portions of the process.

Perhaps best of all is that the whole thing is web-based, so you don't have to mess around installing software on your own computers. Instead, you can access MemQuest over the web and be up-and-running before you know it!

Optimal

In many ways life was so much easier when I was a young ASIC designer circa 1980. Of course we didn't actually have any design tools and we did everything using a pencil and paper, but all we had to worry about was logical functionality and timing. Remember that we're talking about devices with 5nm geometries and clock frequencies in the megahertz range, so we really didn't spend much time worrying about things like signal integrity.

Similarly, we didn't pay any attention to the chip package – that was someone else's problem. And the thought of actually mating the chips we were designing with a circuit board was so far down the line that I don't recall ever considering any issues that might come up.

All that has changed these days; now it's necessary to perform 3D power, signal, and thermal integrity analysis for the chip package – this is especially true for system-in-package (SiP) devices. Furthermore, it's often necessary for design teams to concurrently analyze and optimize the chip together with its package and the packaged chip together with the circuit board.

This makes my head spin, which is why the guys and gals at <a href="http://www.optimalcorp.com" target="_new"Optimal</a> spend their days creating state-of-the-art tools like their flagship PakSi-E, quasi-static electro-magnetic analysis software for IC package, System-in-Package, and printed circuit board design.

Tensilica

I've long been interested in the cunning processor core concept from <a href="http://www.tensilica.com" target="_new"Tensilica</a>. You know the idea; if you're designing an SoC and you need a processor core, you can purchase a general-purpose core from one of the usual suspects. Alternatively, you can generate a high-performance, low-power custom core using the tools from Tensilica. And just to make things really easy, the folks at Tensilica have also used their tools to create a suite of pre-defined "Diamond Standard" cores.

Well, just a few minutes ago as I pen these words, the guys and gals at Tensilica emailed me to tell me that they've just announced the industry's first MP3 decoder to run under 6 MHz. Apparently they've optimized the MP3 decoder for their Xtensa HiFi 2 Audio Engine and Diamond Standard 330HiFi processor core. This MP3 decoder now runs at the lowest power and is the most efficient in the industry, requiring just 5.7 MHz (when running at 128 Kbps, 44.1 KHz) and dissipating only 0.45 mW in TSMC's 65 nm LP process (including memories). This makes this little rapscallion ideal for adding MP3 playback to cellular phones, where current carrier requirements are for 100 hours of playback time on a battery charge (this requirement is expected to increase to 200 hours in the near future).

It's important to note that this 5.7 MHz requirement includes the entire MP3 decode functionality, including MPEG container parsing and variable length decoding (VLD), which is also known as Huffman decoding. (Tensilica informs me that some competing offerings are merely accelerator blocks that exclude portions of the complex control code in MP3 such as VLD, and thus rely on a processor to perform VLD decoding – the little scamps!)

CerTess

Last (for this column) but certainly not least is the news from those little rascals at <a href="http://www.certess.com" target="_new"Certess</a>. In a nutshell, they've recently launched a tool called Certitude (I love these clever product names) that is claimed to be the first tool to enable the Functional Qualification of electronic designs.

Now, your first reaction may be "Huh?" But I didn't say Functional Verification, I said Functional Qualification, which is quite a different kettle of fish! What this means is that – if you are creating a system on a chip (SoC) or intellectual property (IP) block – Certitude will certify that if your design has a bug, that bug will be found.

Certess' patent pending technology, which they say has performed the functional qualification of numerous projects at large semiconductor and systems manufacturers, objectively analyzes, measures and enables the improvement of functional verification environments for complex designs. The way this works is that Certitude is based on a technology known as Mutation Analysis, which – in turn – is based on the concept of introducing atomic changes called mutations into the HDL description of the design; if the change is not detected, it exposes a weakness in the design's verification environment.

There's much more to Certitude than we can go into here, but I personally thing this is a really exciting concept and I will be keeping an eagle eye on this technology.

So Long, Farewell, . . .

Good grief! Is that the time? I have to finish up quickly because John Blyler is bombarding me with emails saying: "I need your Chips and Dips column for the print issue of Chip Design Magazine ASAP". My problem now is that – as soon as I keyed in the title above – the "So long, farewell, . . ." song from The Sound Of Music started rattling round in my head and now it won’t stop. Be careful, it may be catching! I'm too young for all of this (grin)! Until next time, have a good one!