32NM NODE USJ IMPLANT & ANNEALING OPTIONS
John O. Borland
J.O.B. Technologies
98-1204 Kuawa St.
Aiea, Hawaii 96701
For the 32nm node, using msec only dopant activation techniques reveal the potential for serious device variation caused by both single wafer high current implanter design and msec annealing micro-uniformity variation effects. New non-contact metrology techniques with <1mm detection resolution such as RsL (electrical Rs and leakage) and TW (thermal wave dose and damage detection) are required for process optimization to reduce these effects. Also, molecular dopant species (B18H22, P2 & As2) and high mass dopants (Sb) for n & p type SDE and HALO implantation are shown to give highest quality junctions and enhanced dopant activation with msec and SPE diffusion-less annealing techniques. To minimize strain-Si relaxation and high-k/metal gate degradation process integration trade-offs are required.
INTRODUCTION
For the 32nm node the industry will target USJ junction depths from a conservative 20nm down to an aggressive 8nm. Achieving high quality aggressive junctions <10nm will require diffusion-less or <3nm diffusion annealing techniques. There are numerous annealing options available that are dependent on the gate stack structure and process integration flow including: 1) high temperature msec Flash or laser annealing, 2) lower spike annealing temperatures (<900oC), 3) higher SPE annealing temperatures (>700oC) and 4) combinations of spike+msec annealing or msec+spike annealing. These various dopant activation annealing techniques for minimal dopant diffusion must also be compatible with the strain-Si technique to prevent strain relaxation. The implant and annealing USJ process module must be “design for manufacturing” and not increase wafer device variation [1]. Feudel reported on the effects of annealing technique on device Ion variation as shown in Fig. 1 comparing lamp spike, non-lamp spike, Flash and laser annealing techniques [2-4]. Global and local across wafer micro-uniformity variations can be caused by the high current (HC) implanter design in combination with msec annealing equipment due to their unique non-uniformity signatures as shown in Figs. 2 & 3 [5,6].
Fig.1: Ion variation based on annealing method used (spike RTA with and without lamp, Flash and laser) [4].
Fig.2: Unique high current implanter signature after spike annealing detected by high resolution Rs maping of a) batch end station and b) serial end station with quad-mode implant [5].
Fig.3: Full wafer thermal-wave imaging for a) Xe-lamp Flash anneal and b) hot-wall spike anneal [6].
IMPLANT OPTIONS
Single wafer HC implanter replaced batch type due to gate poly yield failure as first reported by Kawasaki [7]. Each HC implant vendor has a different serial wafer end-station design including scanning mechanism resulting in a unique non-uniformity signature caused by local and global variation in implant precision due to dose and angle control. Any variation in localized implant angle will result in asymmetrical transistor, Vt & gate length variation and gate delay degradation as reported by Kuroi [8]. Detecting these HC implant localized micro-variation requires <1mm pitch metrology tool resolution. Fig. 4 shows results from an improved performance Therma-Probe® (TP) metrology system for 100keV arsenic implantation in the E14 to E16/cm2 dose range [9]. Fig. 5 shows full wafer contour maps of a ribbon beam serial HC implant signature for single scan and quad-mode scanning. The corresponding diameter line scan results are shown in Fig. 6 a & b. To improve detectability full wafer imaging thermal-wave (TW) maps are also possible as shown in Fig. 7 [6].
Fig. 4: Improved TP performance to detect high dose implantation [9].
Fig. 5: TW wafer map of ribbon beam with single versus quad-mode scanning.
Fig. 6a: Diameter line scan for single scan mode.
Fig. 6b: Diameter line scan for quad-mode.
Fig. 7: TW full wafer image map for a HC ribbon beam quad-mode implant [6].
The Xj target for the 45nm node is 12-20nm, requiring B energy to be 200-500eV. However, for 32nm node the targeted Xj is between 8-20nm after anneal. This drives the B implant energy down to between 50-100eV, which would produce an as implanted Xj=5-6nm if a pre-amorphizing implant (PAI) is used to prevent boron dopant channeling as shown in Fig.8 [1]. In this range, conventional high current implanters must use decel-mode, which leads to energy contamination. The shallow junction requirement places tight constraints on allowable energy contamination, usually <0.1%, limiting decel ratios to <2 to 1. The BF2 option would require energy in the range of 250-500eV, but residual implant damage, end of range (EOR) defects and other adverse effects of fluorine make this option less desirable [10]. On the other hand using molecular dopant species such as B18H22, the operational energy would be 1-2keV in drift mode and avoid the defect issues with BF2 and PAI+B implants. Another issue for junctions below 10nm is the retained boron dose after implant and annealing, as shown in Fig. 9 [1]. The Bss (boron solid solubility) activation data shown in Fig. 9 is for Flash annealing at >1300oC where a Bss activation level of 1E20/cm3 is realized until the retained dose drops below 6E14/cm2. With a retained dose of 3E14/cm2 an activation level of only 5E19/cm3 is realized for BF2 therefore, at low energies, retained dose and total activation levels varies with each dopant species. Since enhanced B dopant activation was reported when using B18H22 with advanced annealing techniques such as Flash, laser and SPE, retained dose may not be a major concern as it is with BF2 as shown in Fig. 10 [11,12].
Fig. 8: Boron implant energy versus depth.
Fig. 9: Retained boron dose for various B dopant species.
Fig. 10: Enhanced dopant activation with B18H22.
ANNEALING OPTIONS
Starting at the 90nm node several companies have been using spike + msec Flash annealing in production for high performance logic devices for tox inversion reduction [3]. Fig. 11 shows the FEOL roadmap as reported by Feudel of AMD showing spike + msec at 65nm node going to msec only at the 45nm node and beyond [2]. Different Flash equipment results in different dopant activation as shown in Fig. 12 comparing Dai Nippon Screen and Mattson results for B with and without Ge-PAI [13,14]. This explains the differences in dopant activation for B18H22 (9E19/cm3 versus 1.7E20/cm3) reported by Borland when using 2 different Flash annealing equipment shown in Fig. 13 [13]. For arsenic n-type dopant, no difference is seen with or without Ge-PAI for different Flash annealing power settings as shown in Fig. 14a and antimony dopant species looks to be best as shown in Fig. 14b for both Flash and SPE annealing[14,15]. Similar independent results were reported by Mineji comparing As, As2, P2 and Sb as shown in Fig. 5 [12]. P2 was best with flash annealing while Sb was 2nd best but best with SPE.
Fig. 11: AMD dopant activation roadmap [2].
Fig. 12: Comparison of 2 different Flash annealer for B w/wo Ge-PAI for increasing annealing power and temperature [13].
Fig. 13: Direct B18H22 activation comparison [13].
Fig. 14: Flash annealing results for n-type dopants [14,15].
Fig. 15: Comparison of As, As2, P2 and Sb for n-type SDE [12].
When the electrical dopant activation level (Bss) is 10x to 100x below the chemical level, dose variation is not critical and this is especially true for boron with spike annealing and diffusion. With arsenic this difference is only about 2-5x. Also, with soak or spike RTA annealing with >15nm of dopant diffusion, the as-implanted non-uniformity is usually washed out but with diffusion-less activation the as-implanted signature becomes the final after anneal signature, so detection and monitoring of these effects is important. It is also important to know the diffusion-less activation annealer signature which can also contribute to both global and micro-localized device variation as shown in Fig. 16 for PLi, Fig. 17 for TW and Fig. 18 for Rs on wafers that were Flash annealed [16-18]. With Flash only annealing the normalized PLi global wafer variation is 23.6% and local peak to peak variation is 3.7% [16,17]. By adding a 1000oC spike before the Flash anneal reduced global variation to 7.1% and local variation to 1.1% and the Xe-lamp pattern signature could not be seen. Similar wafer image mapping can be seen by TW as shown in Fig. 17 with a global TW variation of 28.6% and micro local lamp peak to peak variation of 5.4% [6]. From the RsL metrology measurements the global variation for the Flash lamp annealing was detected to be 8% and local peak to peak was 1.5% as shown in Fig. 18 [18].
Fig.16: PLi full wafer image comparison for Flash and spike + Flash annealing [16].
Fig. 17: TW full wafer image mapping [6].
Fig. 18: Full wafer RsL map and diameter line scans for Flash annealing [18].
Results for laser annealing is shown in Fig. 19 showing Rs local variation of about 7% due to the laser annealing stitching/overlap pattern effects and localized heating variation as reported by IMEC using u4PP showing a 0.8mm peak to peak variation [19]. IMEC then measured long channel Vt variation and note that a variation of also about 7% was detected and shown in Fig. 20. Therefore IMEC made a 1 to 1 correlation between localized Rs variation to long channel Vt variation.
Fig.19: Rs line scan using u4PP detecting laser annealing localized stitching and heating variation [19].
Fig.20: Vt variation for nMOS and pMOS long channel devices [19].
STRAIN-SI INTEGRATION
At the 45nm node the target strain-Si level is about 1.5GPa and at the 32nm node this increases to 2GPa. There are a number of different methods to induce localized tensile ad compressive strain in the device channel region for mobility enhancement including: 1) CVD stress liners (tensile for nMOS and compressive for pMOS), 2) stress memorization technique, 3) eSiGe S/D for pMOS, 4) eSiC S/D for nMOS, 5) hybrid oriented substrate and 6) STI. However, dislocation formation and strain relaxation with the introduction of msec laser and Flash annealing has been reported by Hyot of MIT and shown in Fig. 21 for a laser annealing example at temperatures 1000oC [20]. To minimize this effect Fig. 22 shows the process flow reported by Eiho using SMT technique were the USJ SDE implant sees 2 spike anneals before the msec anneal step and the SMT process has a spike anneal before the msec anneal step [21]. The trade-off is dopant deactivation versus strain relaxation. An alternative to eSiC SEG is to use C implantation as reported by Liu of IBM and shown in Fig. 23 [22]. Cluster carbon molecular dopant species can also be used as shown in Fig. 24 [23].
Fig.21: Mobility degradation when laser annealing temperature goes above 1000oC [20].
Fig.22: Process integration of SMT strain-Si technique with msec annealing [21].
Fig.23: Carbon implantation to form eSiC strain-Si [22].
Fig.24: molecular carbon dopant for tensile strain-Si technology [23].
HIGH-K/METAL GATE INTEGRATION
For the 32nm node the industry will be using: 1) SiON/poly/metal, 2) medium-k (10-12) HfSiON/metal and 3) high-k (20-25) HfSiOx/metal gate stack structures as shown in Fig. 25. At the 2007 VLSI Symposium panel discussion on high-k/metal gate stacks about 50% of the industry will be moving to Hf-based gate material in various form with k value varying from 8 to 24 using poly, MIPS (very thin Metal Inserted Poly Stack) to thick metal electrodes. If metal is used it can be single metal of dual metal for nMOS and pMOS. Also of note was that no one mentioned using FUSI as a metal gate option. Various process integration flow options will also be used: 1) gate first standard process flow, 2) gate first with disposable spacer process flow (reverse source drain), 3) gate last (replacement gate) process flow or 4) hybrid gate first for one type of MOS transistor and gate last for the other type MOS transistor as reported by Bohr and shown in Fig. 26 [24].
Fig. 25: Options for 45nm and 32nm node gate stack and annealing roadmaps.
Fig.26: Integration options for high-k/metal gate [24].
Spike+msec annealing will be used with poly gate electrode to further reduce tox inversion by 1 to 2 angstrom. Gate first processing can be used with msec annealing with medium-k <16 Hf-based oxide. For high-k >20 gate last processing must be used because the high temperature msec annealing would recrystalize the Hf-oxide degrading the k value unless <800C low temperature annealing like SPE is used then gate first processing can be used without degrading the high-k value.
Tsutsui from NEC mentioned their approach of poly/HfSiON for nFET and poly/TiN/HfSiON for pFET and the HfSiON is formed by depositing a thin layer of Hf on top of SiON shown in Fig. 27 [25]. Chung of Samsung said that gate first is the only option for memory devices for self aligned contacts and he sees three possible gate first approaches for DRAMs [24]. Option #1 is dual poly gate using high-k gate dielectric with n+ ad p+ doped poly electrodes (no metal). Option #2 is for single metal gate and would use high-k/metal for pMOS and high-k/n+ poly for both nMOS and cell transistors. Option #3 is for dual metal gate and would use high-k/metal #1 for pMOS and high-k/metal#2 for nMOS with the gate first approach. Also he said MOCVD would be used for >1.2nm EOT and ALD for <1.2nm EOT. Khare of IBM said they use a very thin single metal with very thick poly on top for the high-k MIPS electrode and they dope the poly back to the desired n+ and p+ Vt targets. Renesas’ approach was very different, they reported using an n+ poly/metal/high-k for pMOS while the nMOS remained poly without the MIPS (n+poly/high-k) [26]. The n+ poly was achieved through an in-situ phosphorus doped poly process and the n+ ploy was used for both nMOS and pMOS gate electrodes and they also used spike RTA + laser annealing. Reducing the interfacial oxide layer from 0.8nm to 0.4nm and increasing the k value from 12 to >20 is key to continue gate EOT scaling at the 32nm node and beyond.