Even Parity Bit Generator

Aim:

The aim of this project is to design a 3-bit even parity generator that can detect a one-bit error in a message and draw the CMOS layout in L-Edit, which can then be simulated using PSPICE.

Abstract:

An even parity bit generator generates an output of 0 if the number of 1’s in the input sequence is even and 1 if the number of 1’s in the input sequence is odd. The checker circuit gives an output of 0 if there is no error in the parity bit generated. Thus it basically checks to see if the parity bit generator is error free or not.

Schematic:

The design procedure is made simple by writing the truth table for the circuit.

Truth table:

Message Even parity bit Checker bit

X Y Z P C

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 0

1 0 0 1 0

1 0 1 0 0

1 1 0 0 0

1 1 1 1 0

The circuit can now be derived by drawing the K-map for the output.

From this the minimal output equation is

This function can be implemented using exclusive-or gates. The schematic of the parity generator circuit is shown in Figure 1.

Figure 1: Parity bit generator

Similarly the checker circuit can be designed using XOR gates, where and the circuit is shown in Figure 2.

Figure 2: Checker circuit

Now the parity bit generator and the checker circuit can be combined into one circuit for simplicity. The final schematic of the circuit is shown in Figure 3.

Figure 3: Combined schematic of both parity bit generator and checker circuit

The final layout consists of four XOR gates, which can be designed, in L-EDIT using the CMOS technology. The basic building blocks in CMOS technology are MOSFET’s. A MOSFET is a metal oxide semiconductor field effect transistor. The advantages of MOSFET over BJT’s are, they are smaller in size and the drain and source terminals are interchangeable. This provides the designers with area minimization on the chip.

Software used:

1. L-EDIT student version for drawing the layouts.

2. PSPICE for simulating the layouts.

Basic building blocks:

MOSFET’s are the basic building blocks. There are three main components to a CMOS transistor. The Source and Drain can be interchanged at the silicon level and occasionally at the device level. These are the main current carrying terminals. The Gate is separated from the Composite (Silicon) by a thin layer of SiO2, which acts as an insulator or dielectric. In the CMOS world you can create a Capacitor by shorting the Source and Drain together calling that one terminal, and using the Gate for the other terminal. The difference between an NMOS and a PMOS device depends on the type of WELL (base) the transistor is sitting in.The layout of a p-channel MOSFET drawn in L-Edit is shown in Figure 4. Layout of a MOSFET using L-Edit is very straightforward. An n-channel device is constructed by creating an n+ region ndiff defined by

ndiff = (ACTIVE) AND (NSELECT)

A POLY over ndiff creates the transistor. The drawing steps for creating the nFET are as follows.

1. Construct an ACTIVE box/polygon.
2. Surround ACTIVE with NSELECT. The intersection of the two is ndiff.
3. Create a POLY box that crosses completely over ndiff and extends beyond the ACTIVE area. This creates the gate.

The actual drawing sequence is not important. However, all design rules should be obeyed. Figure 4 shows the layout of an nMOSFET structure. Each layer is drawn sequentially obeying all the design rules and a DRC is performed to check if there are any errors in the layout design.

Figure 4: nMOSFET

Figure 5 shows that nMOSFET is constructed without violating any design rules.

Figure 5: DRC file for Figure 4

Figure 6 is the Extraction definition file for the layout in Figure 4.

Figure 6: Extract definition file for layout in Figure 4

A p-channel MOSFET follows the same basic order, except that the n-well must be defined. The steps are:

1. Create an NWELL region for the pMOSFET.
2. Construct an ACTIVE box/polygon for the transistor.
3. Surround ACTIVE with PSELECT. The intersection of the two is pdiff.
4. Draw a POLY box over pdiff for the gate.
5. Provide an ACTIVE and NSELECT box within NWELL for the n-well contact (to VDD)

Note that the n+ contact formed in step 5 is needed to bias the n-well to the power supply voltage.

Figure 7 shows the layout of a pMOSFET. Design is constructed sequentially by performing DRC at each stage.

Figure 7: pMOSFET

Figure 8 shows the DRC file for a pMOSFET. All design rules are obeyed.

Figure 8: DRC file for Figure 7

Figure 9 shows the extraction definition file for the layout in Figure 7.

Figure 9: Extract definition file for layout in Figure 7

The definition files are extracted using the morbn20.ext file, which gives the information about the transistors and the corresponding nodes and parasitic capacitances. This is used as a netlist in the PSPICE to generate the output waveform.

Procedure:

Any layout in L-Edit can be drawn using these two transistors. In this project, four XOR gates are needed which can be built from the basic transistors. It is important to understand the schematic of an XOR gate. A simple XOR gate can be built using two inverters and two transmission gates.

CMOS Inverter:

The schematic of a CMOS inverter circuit is shown in Figure 10. It consists of a p-FET and an n-FET connected back in the form of a complimentary pair. The gates of the two transistors are connected to the input pulse and the inverted output pulse is obtained at the point where the source of the p-FET is connected to the drain of the n-FET. When the input pulse is at 0 level, the p-FET turns ON and the DC voltage VDD is observed at the output. When the input is at HIGH level, the n-FET turns ON and the ground voltage 0 is observed at the output.

Figure 10: CMOS Inverter

The layout of an inverter in L-Edit is shown in Figure 11.

Figure 11: Inverter layout

The .SPC file is extracted from this layout, which is shown in Figure 12. This file indicates that there are two transistors in the layout i.e., M1 and M8. The line M1 11 3 10 PMOS indicates the nodes for the p-MOSFET in the order Drain Gate Source. By observing the node numbers for both the transistors we can say that node 3 is the common gate where the input pulse is to be given and node 10 is the common point where output is obtained. Voltage VDD is given at node 11 and VSS is given at node 9. By using this information a .CIR file can be created wherein the values for these voltages are specified at corresponding nodes.

Figure 12: .SPC file for inverter

The .cir file for an inverter is shown in Figure 13.

Figure 13: .CIR file for an inverter

The lines VDD 11 0 DC 5 and VGND 9 0 DC 0 indicate the voltages between the starting node and ending node and DC specifies the type of voltage given. The general format of these lines can be written as

Node_ name starting_node ending_node voltage_type value

The next line in the .cir file indicates the pulse voltage given at the input. The general format for this type of input is

Node_ name starting_node ending_node PULSE (low_value high_value td tr tf tp T)

Here td is the time delay, tr is rise time, tf is fall time, tp is the pulse width and T is the time period of the pulse. L-edit consists of a file SCNA.SPC which defines the dot model parameters for the transistors. This file has to be included in the .cir file. Lastly, .TRAN 2ns 20ns indicates the type of simulation i.e., in this case it is the transient analysis. The general format for this is

.TRAN step_size simulation_time

Finally the .PROBE line specifies the output probe in the layout. This file is compiled in the PSPICE A_D. The input and the output pulses are observed by running the probe in PSPICE. The PSPICE simulation of the inverter is shown in Figure 14.

Figure 14: PSPICE simulation of an inverter

Transmission gate:

A transmission gate consists of a PMOS and an NMOS connected in a way that input is transmitted in one condition and blocked in other condition. The schematic of a transmission gate is shown in Figure 15.

Figure 15: Transmission gate schematic

The operation of a transmission gate is as follows: when S is LOW, both PMOS and NMOS are OFF and the input A is not transmitted to the other end. When S is HIGH, both PMOS and NMOS are ON allowing A to pass through the gate. Figure 16 shows the layout of a transmission gate in L-Edit.

Figure 16: L-Edit layout of transmission gate

The extraction and simulation steps are the same for every layout and thus are repeated for the transmission gate. The .cir file and the PSPICE simulation of the transmission gate are shown in Figures 17 and 18 respectively.

Figure 17: .cir file for transmission gate

Figure 18: PSPICE simulation of transmission gate

XOR gate using inverters and transmission gates:

The XOR gate consists of two inverters and two transmission gates. The schematic of XOR gate is shown in Figure 19.

Figure 19: Schematic of XOR gate

The layout of XOR gate in L-Edit is drawn by creating the basic cells. The transistors are used as instances in drawing the layouts of inverter and transmission gates. This feature is available in L-Edit in the cell menu. The cells are then flattened. Now by using the inverter and transmission gate as instances the XOR layout is completed. Figure 20 shows the layout of XOR gate in L-Edit. Two inverters are used since we need both A’ and B’ in the XOR function. The .CIR file in Figure 21 shows that there are 8 transistors in the XOR gate. The output of an XOR gate is 0 when both the inputs are same. This can be observed in the PSPICE simulation waveforms obtained for this layout. The waveforms are shown in Figure 22.

Figure 20: Layout of XOR gate in L-Edit

Figure 21: .CIR file for XOR layout

Figure 22: PSPICE simulation of XOR layout

Complete layout of the parity bit generator and checker circuit:

The layout of a parity bit generator/checker circuit consists of four XOR gates. Thus, XOR cell is created which is used as instance to build the complete layout. Each XOR gate consists of 8 transistors, therefore the complete layout consists of 32 transistors. The limitation of PSPICE student version software is that it cannot simulate more than 10 transistors. Thus the complete layout cannot be simulated with this version. The extracted file for the layout shows that there are 32 transistors in the layout. Figures 23 and 24 show the L-Edit layout and the extracted file for the project.

Figure 23: L-Edit layout of parity bit generator/checker

* Circuit Extracted by Tanner Research's L-Edit V5.13 / Extract V2.06 ;

* TDB File C:\PARITY, Cell Cell0, Extract Definition File C:\MORBN20.ext ;

C17 119 0 31.291FF

C18 112 0 31.291FF

C19 105 0 31.291FF

C20 99 0 31.291FF

C37 123 0 30.303FF

C38 122 0 30.303FF

C39 121 0 30.303FF

C40 120 0 30.303FF

C41 118 0 14.065FF

C42 116 0 44.08FF

C43 115 0 27.057FF

C44 113 0 163.473FF

C45 111 0 14.065FF

C46 109 0 48.372FF

C47 108 0 27.057FF

C48 106 0 20.996FF

C49 104 0 14.065FF

C50 102 0 60.668FF

C51 101 0 27.057FF

C52 98 0 14.065FF

C53 96 0 27.057FF

C54 94 0 20.996FF

M1 119 109 118 4 PMOS L=2U W=14U

M2 113 109 116 7 PMOS L=2U W=13U

M3 115 118 116 11 PMOS L=2U W=13U

M4 119 113 115 15 PMOS L=2U W=14U

M5 112 102 111 19 PMOS L=2U W=14U

M6 106 102 109 22 PMOS L=2U W=13U

M7 108 111 109 26 PMOS L=2U W=13U

M8 112 106 108 30 PMOS L=2U W=14U

M9 105 106 104 33 PMOS L=2U W=14U

M10 113 106 102 36 PMOS L=2U W=13U

M11 101 104 102 40 PMOS L=2U W=13U

M12 105 113 101 44 PMOS L=2U W=14U

M13 99 47 98 48 PMOS L=2U W=14U

M14 94 47 113 51 PMOS L=2U W=13U

M15 96 98 113 55 PMOS L=2U W=13U

M16 99 94 96 59 PMOS L=2U W=14U

M57 123 109 118 93 NMOS L=2U W=13U

M58 115 109 116 93 NMOS L=2U W=13U

M59 113 118 116 93 NMOS L=2U W=13U

M60 123 113 115 93 NMOS L=2U W=13U

M61 122 102 111 93 NMOS L=2U W=13U

M62 108 102 109 93 NMOS L=2U W=13U

M63 106 111 109 93 NMOS L=2U W=13U

M64 122 106 108 93 NMOS L=2U W=13U

M65 121 106 104 93 NMOS L=2U W=13U

M66 101 106 102 93 NMOS L=2U W=13U

M67 113 104 102 93 NMOS L=2U W=13U

M68 121 113 101 93 NMOS L=2U W=13U

M69 120 47 98 93 NMOS L=2U W=13U

M70 96 47 113 93 NMOS L=2U W=13U

M71 94 98 113 93 NMOS L=2U W=13U

M72 120 94 96 93 NMOS L=2U W=13U

.MODEL NMOS NMOS LEVEL=2 LD=0.250000U TOX=417.000008E-10

+ NSUB=6.108619E+14 VTO=0.825008 KP=4.919000E-05 GAMMA=0.172

+ PHI=0.6 UO=594 UEXP=6.682275E-02 UCRIT=5000

+ DELTA=5.08308 VMAX=65547.3 XJ=0.250000U LAMBDA=6.636197E-03

+ NFS=1.98E+11 NEFF=1 NSS=1.000000E+10 TPG=1.000000

+ RSH=32.740000 CGDO=3.105345E-10 CGSO=3.105345E-10 CGBO=3.848530E-10

+ CJ=9.494900E-05 MJ=0.847099 CJSW=4.410100E-10 MJSW=0.334060 PB=0.800000

.MODEL PMOS PMOS LEVEL=2 LD=0.227236U TOX=417.000008E-10

+ NSUB=1.056124E+16 VTO=-0.937048 KP=1.731000E-05 GAMMA=0.715

+ PHI=0.6 UO=209 UEXP=0.233831 UCRIT=47509.9

+ DELTA=1.07179 VMAX=100000 XJ=0.250000U LAMBDA=4.391428E-02

+ NFS=3.27E+11 NEFF=1.001 NSS=1.000000E+10 TPG=-1.000000

+ RSH=72.960000 CGDO=2.822585E-10 CGSO=2.822585E-10 CGBO=5.292375E-10

+ CJ=3.224200E-04 MJ=0.584956 CJSW=2.979100E-10 MJSW=0.310807 PB=0.800000

.TRAN 2ns 20ns

.PROBE

.END

Figure 24: .CIR file for the parity bit generator/checker

Application of parity bit generator circuit:

Parity bit generator is used in digital communications where the messages are transmitted in the form of 1’s and 0’s. In communications, a message has to be transmitted between two points without any loss or errors. This is done by checking the message bits at the transmitter end and the receiver end. A parity bit is generated at the transmitting end and is transmitted along with the message bits through the transmission channel. At the receiving end the parity bit is again generated and is checked against the parity bit generated at the transmitter. If both are the same then the message is error free else the message is different from the transmitted message. Note that this method only helps in detecting a one-bit error in message sequence but it does not correct the message. This is one of the many error detection methods used in digital communications.

References:

1. Physical Design of CMOS Integrated circuits using L-Edit by John P.Uyemura.

2.Circuit Design for CMOS VLSI by John P.Uyemura.

3.

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