Glacier Journal Of Scientific Research ISSN :2349-8498
High performance low leakage CMOS multiplier using 65nm technology
Sona Rani Candy Goyal
Deptt.of Electronics and Communication Deptt.of Electronics and Communication
Yadavindra College of Engineering Yadavindra College of Engineering
Talwandi Sabo, India Talwandi Sabo, India
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Glacier Journal Of Scientific Research ISSN :2349-8498
Abstract—Multiplication is an important fundamental function in arithmetic operation. In this paper we present different types of 8-bit multiplier name as Braun multiplier, Wallace tree multiplier, Row bypass Braun multiplier, Column bypass Braun multiplier, Row and Column bypass Braun multiplier with and without control signal. All these multipliers are compared in terms of delay, power dissipation, power delay productand leakage power. These multipliers are simulated using Tanner v13.0 at 1GHz frequency with 65nm technology with a supply voltage 1.0v. Simulation results show that the Braun multiplier with control signal using bridge style adder has minimum power delay product and Wallace tree multiplier with control signal has least leakage power.
Keywords:- VLSI, CMOS, PDP, multiplier
I. INTRODUCTION
Multipliers play an important role in today’s digital signal processing and various other applications.Multipliers are responsible for slowed speed and consume considerable power. Hence, it is very important for modern DSP systems to develop low-power multipliers to reduce the power dissipation and improve performance. Therefore low-power multiplier design has been an important part in modern VLSI system design [1]. In modern VLSI circuits, low-power and high-speed are the two parameters which must be considered. Also these low power design systems reduce cooling cost and increase the reliability of systems. The increasing demand for low-power VLSI can be addressed at different design levels, such as the architectural, circuit, layout, and the process technology level. There is always a trade-off between the various design parameters such as speed, power consumption, and area [2].
There are different multiplier structures which can be classified as Serial Multipliers, Parallel multipliers, Array multipliers, Tree multipliers and so on [3]. A number of approaches have been adopted to implement a multipliercircuit with low transistor count, low power consumption, high speed responseetc. The basic and typical array multiplier performs multiplication by arranging the full-adders to add the partial products for each output bit. The logicalcircuit diagram of bridge style full adder [4] is
Fig.1 Bridge style Full adder
The power consumption of a CMOS transistor can be divided into three different components: dynamic, static and short circuit power consumption [5]. Dynamic and short circuit power are also collectively known as switching power. Leakage or static power is consumed merely because the circuit is “powered-on”. Switching power is consumed when signals through CMOS circuits change their logic state, resulting in the charging anddischarging of load capacitors. Leakage power is primarily due to the sub-threshold currents and reverse biased diodes in a CMOS transistor. Thus,
Ptotal= Pdynamic+Pshort_circuit+Pleakage
= V2dd.fclk.CL.α + α/12(Vdd – 2Vth)3 tr/tf + IleakageVdd
Where fclk is the system clock frequency, CL is the load capacitance, α is the switching activity factor, tr/, tf is the rise and fall time of input signal, Ileakageis the total leakage current flowing through the device [6].As technologies scaled down leakage power isincreased as compare to dynamic power [7]. Leakage power dissipation is divided in two major parts, the sub-threshold leakage and the gate-oxide leakage. The sub-threshold leakage is caused by short channel effects and low threshold voltage (Vth), while the gate-oxide leakage is exponentially increasing with the decreasing oxide thickness. As in each new technology the supply voltage decreases to improve performance and dynamic power dissipation, this requires the threshold voltage being scaled down also. Unfortunately, sub-threshold leakage currents increase exponentially with decreasing threshold voltage [8].
In this paper we present multiplier names are Array multiplier, Braun multiplier, Wallace tree multiplier, Row bypass Braun multiplier, Column bypass Braun multiplier and Row and column bypass Braun multiplier with and without control logic. A control signal is used to control the leakage power dissipation.
II.TYPES OF CMOSMULTIPLIER
A. Braun multiplier
Braun multiplier is an simple parallel multiplier and generally known as carry save array multiplier and an n bit Array multiplier has n x n array of AND gates to generate partial products, n x (n-2) full adders and n half adders. It has regular structure. Therefore it is easy to design the layout. In VLSI designs, it is easy to design regular structures.This reduces layout design time. This regular layout is widely needed in VLSI math co-processors design and DSP chips design[9].
B. Wallace tree multiplier
A Wallace multiplier consists of two parts: a Wallace Tree for reducing and combining the partial products, and a Final Adder to generate the actual product [10]. In a Wallace multiplier, the number of partial products generated is the same as in the Array Multiplier. Thus there are still N2 AND gates required for an N-bit by N-bit multiplication. The difference lies in the way the partial products are added together in the Wallace tree.Wallace tree has a logarithmic circuit delay and the array multiplier has linear delay. Sodelay of Wallace tree multiplier is near optimal, but layout is irregular. This architecture is used where speed is the main concern not the layout regularity.
C. BraunMultiplier with Row Bypassing
Multiplier with bypassing technique[11] means turn off some columns or rows or both in the n x n bit multiplier whenever certain multiplier or multiplicand or both bits are zero. In Row bypassing technique whenthe multiplier bits are zerothen that particular rows of adders in the basic multiplier array are disabled during operation to save the switchingpower.The Braun multiplier with row bypassing uses additional tri-state buffers and multiplexers in order to skip the FA cell in rows of zero bits. In the multiplier design, each FA is attached by three tri-state buffers and two 2-to-1 multiplexers to bypass the required row as shown in Fig. 2, Fig. 3 respectively. The extra correcting circuits must be added to correct the multiplication result because the rightmost FAs in the rows are able to bypass or must be disable so output is fed to next row.
Fig. 2Circuit Diagram of Tristate Buffer
Fig. 3 Circuit Diagram of 2:1 Mux
D. Braun Multiplier with Column Bypassing
In column bypassing technique a column can be disabled if the corresponding bit in the multiplicand is 0. There are two advantage of this method. First, it eliminates the extra correcting circuit. Secondly, the modified FA is simpler than that of used in the row bypassing multiplier. The modified FAis only attached by two tri-state buffers and one 2-to-1multiplexer [12]. So it uses less hardware as compare to row bypass multiplier.
E. Braun Multiplier with Row and Column Bypassing
In Row and Column Bypassingtechnique the addition operation in the FA can be bypassed if the product, aibj, is 0 and the carry bit, ci,j-1, is 0, that is, as the product, aibj, is 1 or the bit, ci,j-1, is 1, the addition operation in the (i+1, j) FA can be executed[13].The HAs in the first row of CSAs, are also replaced with the incremental adder, A+1,and it is only attached by one tri-state buffer and two 2-to-1 multiplexers.The carry bit in the (i+1, j) FA can be replaced by the AND result of the product, aibj, and the bit, ci,j-1, and the (i+1, j) FA, n > j > 1, can be replaced with the A+B+1 adder and it is attached by two tri-state buffers and two 2-to-1 multiplexers.
Fig. 4 A+1 adder
Fig. 5 A+B+1 adder
III.MULTIPLIER DESIGN WITH LOW LEAKAGE POWER
In this section, we design multiplier with control signal in order to reduce leakage power.In this paper, a full adder cell is composed of some extra footer cell to make the circuit faster and low power dissipation [14]as shown in fig. 6. It has the less leakage power consumption and less power delay product (PDP) as compared withconventional static adder. Due to the minimum time delay of sumand carry out, the adder core greatly progress the overallperformance of multipliers. Circuit diagram of different multiplier design are shown in Fig.7to Fig. 11.
Fig. 6 Circuit Diagram of bridge style one bit full adder with control signal
Fig. 7Circuit Diagram of 8-bitBraun multiplier with control signal
Fig. 8 Circuit Diagram of 8-bitWallace tree multiplier with control signal
Fig. 9Circuit Diagram of 8-bit Row BypassBraun Multiplier with control signal
Fig. 10 Circuit Diagram of 8-bit Column Bypass Braun multiplier with control signal
Fig. 11 Circuit Diagram of 8-bit Row and Column Bypass Braun multiplier with control signal
IV. ANALYSIS OF MULTIPLIER
Different types of 8-bit multipliers are compared named as Array multiplier, Braun multiplier, Wallace tree multiplier, Row bypass Braun multiplier, Column bypass Braun multiplier and Row and Column bypass Braun multiplier by using bridge style one bit adder with and without control signal. All the simulations are performed at using 65nm technology, a 1V power supply at frequency of 1GHz. All circuit logic style is designed using different gate width of NMOS and PMOS and with a minimum length of 65nm for NMOS and PMOS. Simulations are performed using HSPICE.All result of different multipliers are summerised in the form of table which are described below:-
Table1: Average Power dissipation of 8-bit multipliers at 1.0v.
Type of Multiplier / Frequency (1GHz)Power(mW)without control signal) / Power(mW) (with control signal)
Braun Mul / 20.905 / 9.623
Wallace Tree Mul / 20.791 / 8.695
Row Bypassing Braun Mul / 48.242 / 23.364
Column Bypassing Braun Mul / 41.888 / 19.437
Row And Column Bypassing Braun Mul / 52.023 / 25.153
Table2: Delay of 8-bit multipliers at 1.0v.
Type of Multiplier / Frequency (1GHz)Delay (ns) (without control signal) / Delay(ns)(with control signal)
Braun Mul / 0.361 / 0.527
Wallace Tree Mul / 0.844 / 0.842
Row Bypassing Braun Mul / 0.409 / 0.566
Column Bypassing Braun Mul / 0.412 / 0.376
Row And Column Bypassing Braun Mul / 0.413 / 0.422
Table3: Power Delay Product of 8-bit multipliers at 1.0v
Type of Multiplier / Frequency (1GHz)PDP(pJ) (without control signal) / PDP(pJ) (without control signal)
Braun Mul / 7.546 / 5.071
Wallace Tree Mul / 17.547 / 7.321
Row Bypassing Braun Mul / 19.731 / 13.224
Column Bypassing Braun Mul / 17.258 / 7.308
Row And Column Bypassing Braun Mul / 21.485 / 10.614
Table 4: Transistors Count of 8-bit multipliers
Type of Multiplier / Transistor Count without control signal / Transistor Count with control signalBraun Mul / 1648 / 1785
Wallace Tree Mul / 1648 / 1776
Row Bypassing Braun Mul / 5046 / 5188
Column Bypassing Braun Mul / 3622 / 3759
Row And Column Bypassing Braun Mul / 4196 / 4352
Table5: Leakage power of 8-bit multipliers
Type of Multiplier / Leakage Power (mW)without control signal / Leakage Power(mW)with control signal
Braun Mul / 0.16 / 0.07
Wallace Tree Mul / 0.15 / 0.06
Row Bypassing Braun Mul / 35.94 / 3.41
Column Bypassing Braun Mul / 17.92 / 3.32
Row And Column Bypassing Braun Mul / 30.33 / 32.34
Fig.12 Comparison of PDP for different 8 bit multiplier at 1GHz
Fig. 13 Comparison of Leakage Power for different 8 bit multipliers
V. CONCLUSION
Result shows that the Braun multiplier with control signal using bridge style adder has 32.80% less PDP as compared to Braun multiplier without control signal and it has minimum PDP as compared to the other multiplier analyzed. Wallace tree multiplier with control signal has 57.37% less leakage power as compared to Wallace tree multiplier without control signal and it dissipate less leakage power among all the other multiplier analyzed. Power delay products of Braun multiplier with control signal is 5.07462pJ at frequency 1GHz. Leakage power of Wallace tree multiplier is 66.63µW.
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