May 4-5, 2011 Dana Point, CA, USA

Held in Conjunction with IEEE VLSI Test Symposium (VTS 2011)

Call for Papers

Committee
General Chairs
Michael Nicolaidis, TIMA
Yervant Zorian, Synposys
Vice General Chairs
Adit Singh, Auburn U.
Rajesh Galivanche, Intel
Program Chairs
Dimitris Gizopoulos, U. Piraeus
Virendra Singh, IISc,
Vice Program Chair
Sreejit Chakravarty, LSI
Finance Chair:
Nacer-Edine Zergainoh, TIMA
Publicity Chair:
Yiorgos Makris, Yale U.
Panels Chair
Subhasish Mitra, Stanford U.
Publications Chair:
Mihalis Psarakis, U. Piraeus
Program Committee
TBD / Objectives
As silicon based CMOS technologies are fast approaching their ultimate limits, reliability is threatened by issues such as process, voltage and temperature variability, accelerated aging and wearout, radiation induced soft-errors and cross talk. In particular, variability of process, voltage and temperature represent a significant threat not only for parametric yield but also for reliability, since they induce timing faults that are extremely difficult to detect during manufacturing testing. It results on increasing ratio of circuits passing fabrication test that are susceptible to manifest failures in the field.
These problems are creating barriers to further technology scaling and are forcing the introduction of new process, design and test solutions aimed at maintaining acceptable levels of reliability. As elimination of these issues is becoming increasingly difficult, various design techniques are emerging to circumvent them. These techniques may incur area, power, yield or performance penalties. Thus, to enable their adoption by the industry there is need for novel solutions to minimize penalties and provide automation tools.
The goal of this workshop is to create an informal forum to discuss those design, EDA and test innovations enabling chips to maintain acceptable reliability levels at reasonable cost. The workshop is sponsored by the IEEE Computer Society Test Technology Technical Council.
Representative topics include, but are not limited to:
ü  Reliability issues in advanced CMOS
ü  Variability-aware design
ü  Radiation effects in advanced CMOS
ü  Design for reliability in advanced CMOS
ü  Fault tolerant architectures
ü  Variability mitigation
ü  Self-calibrating architectures
ü  On-line monitoring of circuit parameters
ü  Design automation for self-calibrating and fault tolerant architectures
ü  Variability insensitive architectures
ü  Reliability assessment tools
Submissions To present at the Workshop, authors are invited to submit previously unpublished technical proposals. The proposals may be draft presentations, extended abstracts (500 words), or full papers. Each submission should include: title, full name and affiliation of all authors, a short abstract of 50 words, and keywords. Also, identify a contact author and include a complete correspondence address, phone number, fax number, and e-mail address. Submit a copy of your proposal by PDF either online or via E-mail to :
Proposals for panel discussions are also invited.
Submissions are due no later than March 21, 2011. Authors will be notified of the disposition of their presentation by April 8, 2011. Authors of accepted presentations must submit the final presentation by for inclusion in the Workshop Proceedings, which will be provided to the attendees on a memory stick. Optionally, an extended abstract or paper can also be included in the notes.
General Information
Michael Nicolaidis, TIMA Laboratory / Yervant Zorian, Synopsys
Tel: +33476575060
Email: / Tel: +1 (650) 584-7120
Email:
Program Related Information
Dimitris Gizopoulos, U. Piraeus / Virendra Singh, IISc, Bangalore
Tel: +30210 414 2372
Email: / Tel: +91-80-2293-3421
Email:
For all updated information please visit the DRVW web site: http://tima.imag.fr/conferences/drvw/index.htm