ConcordiaUniversity, Department of Electrical and Computer Engineering

Midterm,Oct. 17, 2005

Answer all Questions. All Questions carry equal marks

Exam Duration 1 hour

No books, papers or calculators are allowed.

======

Question 1

a) Design an 8 bit Manchester Carry adder. Give all gates and signals required for generation of this adder.

b) Determine its frequency of operation assuming a transistor has a delay of Dt, and any gate has a delay of Dg.

Question 2

a) Design a multiplier to calculate - 5A. A is a signed 6 bit number A5 A4 A3 A2 A1 A0.

Give a complete circuit diagram. You may use any method you wish, however your design should be optimum.

b) Estimate delay and area of your design assuming the following

Dfa is the delay of full adder,

Dha is the delay of half adder,

Afa is the area of full adder,

Aha is the area of half adder

Dg and Ag are the delay and area of any gate used.

Question 3

a) Represent A= -3.25, B=18.0 in IEEE 754 format.

b) Perform A* B operation

c) Describe the round to the nearest even rounding scheme used in IEEE 754 standard.

Solutions Midterm exam. Fall ’05

Question 1.

In order to speed up the carry propagation of the carry ripple adder, use is made of 3 parameters:

- carry propagate

- carry generate

- carry delete

Delay of this unit is 1 gate delay, ignoring the inverters.

Area = 3 gates, ignoring the inverters.

To generate the carry than, any of the following cells can be used:

Now a Manchester carry Adder consists of cascaded stages of M-cells. But the optimum amount of cascaded stages in our case can be determined from technology parameters. In most cases four stages is around optimum. Therefore we will separate two stages of 4-bit adder by 2 buffers for simplicity.

In each case then a sum is generated by

General diagram:

Critical Path:

Delay=1DG+8DT+1DG = 2DG+8DT (ignoring inverter delays)

Frequency=

Question 2.

For this multiplier we have signed numbers. However, we have option of selecting representation of the signed number. Since one of the operands is (–5), than a sign and magnitude representation would produce a simple and quick answer. Alternatively, we can use one of many standard signed number multiplication algorithms such as Booth Algorithm or Bough Wooly. In this solution two methods are given:

1)sign and magnitude representation and

2)using Booth with 2’ complement representation.

1) Sign and Magnitude.

(-5): sign = -1; magnitude = 0101;

A: sign = A5; magnitude = A4 A3 A2 A1 A0;

The sign of result is

Magnitude of result:

Delay = 2DFA+3DHA;

Area = 2AFA+3AHA+ 1inverter.

2) Using 2’ complement: (-5) = 1011 = {10110: 101=-1; 110=-1} = (-1)(-1)

Delay = 7DFA + 1DHA;

Area = 7AFA + 9AHA+ 6Ainv.

Question 3.

A=-3.25 = -11.01 = 1.101 *21;

exp = 1 + 127 = 128 = 0111 1111b + 1b = 1000 0000b.

23
1 / 1000 0000 / 1010 0000 0000 0000 0000 000

A

B = 18.0 = 010010.0 = 1.0010 *24;

exp = 4+127 = 131 = 0111 1111b + 100b = 1000 0011b.

0 / 1000 0011 / 0010 0000 0000 0000 0000 0000

B

A * B:

XOR sign bits: ;

Add exponents and subtract bias:

exp = 1000 0000 + 1000 0011 – 0111 1111 = 1000 0100;

Multiply significands:

1 / 1000 0100 / 1101 0100 0000 0000 0000 0000

Result:

Rounding: When R*(M0+S) is true then significand = significand + 0.01

In table format this

x0.00 /  / x0. / x1.00 /  / x1.
x0.01 /  / x0. / x1.01 /  / x1.
x0.10 /  / x0. / x1.10 /  / x1.+1
x0.11 /  / x1. / x1.11 /  / x1.+1
M22 … M1 / M0 / R / S