Take Home Midterm #2: POWER CONSUMPTION AND PROCESS MISMATCH

OUT: Feb. 21;

IN: Mar. 5

DONE INDIVIDUALLY, NOT IN GROUPS

I acknowledge, that I did this work on my own, and did not copy or plagiarize the information from any other people or sources. I sign this to be true, and my signature with my name means I did this work honorably.

NAME: ______

SIGNATURE:______

DATE:______

Optimal Power Consumption vs. Process Sensitivity/Mismatch

Everything we’ve done so far assumes we want the fastest delay. However, for some applications, we need the maximum delay possible and the minimum power consumed. This is a real-time requirement. This is true for: ultra-low power, portable electronics. I.e. sensor networks, portable electronics, etc.

Therefore, As you are the CTO of a sensor networking startup, you need to understand the power consumption valuesfor a XOR-2. Assume the XOR-2 characterization is general enough that you can generalize your results for any logic gate in any technology. Simulate only in simple schematic form. Assume minimum-type sizing for XOR-2 gate. Automate this as much as possible through scripting (i.e. Python; PERL), so you don’t waste too much time. Do this only for TT corner.

AUTOMATION SCRIPT (Tom Ruggeri, Feb. 2011): Here is a script, written by graduate student Tom Ruggeri, that automates this simulation across multiple processes. It was originally written for a D-FF, so you’ll have to adapt it to work for the XOR-2 you have the schematic for.

(Energy dissipated is: integral of Idt / C)

Problem #1: Energy-Delay Product for Scaled Vdd Technologies with NO Process Mismatch

Tplh / Tphl / Td(avg) / I(static) / Energy(static) / Energy(dynamic) / Energy(TOT)/computation
0.25u(2.5V)
2.5V
1.0V
0.6V
0.5V
0.3V
65nm(1V)
1.0V
0.7V
0.5V
0.4V
0.3V

1)PLOT: 1) DELAY vs. VDD for each process; 2) ENERGY/COMPUTATION vs. VDD for each process; 3) ENERGY*DELAY Product vs. VDD for each process(EDP on Y-Axis; VDD and process node on X-Axis)

NOTE: ENERGY(TOT) is the total energy consumed (static AND dynamic) in any one clock period. This is equivalent to ENERGY consumed / computation. YOU NEED TO FIND STATIC ENERGY CORRECTLY, and also what the cycle time is.

Process Variation

In any “real design”, devices, capacitances, resistances, and transistors do not appear as they seem. In actuality, they obey statistical variations in delay, making the behavior extremely difficult to predict. While traditionally we’d like to do a Statistical Methodology (Monte Carlo) for variation simulation/prediction, this is difficult. A more simpler way is to implement a worst-case simulation for the variation. There are two offsets possible in a process: 1) Vt Variation; 2) channel length modulation. Vt variation is characterized as: Sigma(Vt)=Avt / sqrt(W*L), where Avt ~ 2mV/um in general for most technologies. (Pelgrom’s mismatch model)

For this part, still use your XOR-2 gate, but make the worst possible Tplh and Tphl conditions. For example, the worst case Tphl is when: PMOS has smaller Vt; NMOS has larger Vt; process corner is Slow PMOS; Fast NMOS. The converse case (for Tplh) is also true, and needs to be simulated. (NOTE: Ignore the 10% gate length variation for this portion (to simplify your simulations). Just make a sigma- Vth increase (worst-case) in both the NMOS and PMOS of the FA delay, assumingW/L scaling across process technology.

Problem #2: Energy-Delay Products for Scaled Vdd Technologies with WORST-CASE Process Mismatch

Tplh / Tphl / Td(avg) / I(static) / Energy(static) / Energy(dynamic) / Energy(TOT)/computation
0.25u(2.5V)
2.5V
1.0V
0.6V
0.5V
0.3V
65nm(1V)
1.0V
0.7V
0.5V
0.4V
0.3V

1)PLOT: 1) DELAY vs. process; 2) ENERGY(TOT) vs. process; 3) ENERGY(TOT)*Delay Product vs. process (EDP on Y-Axis; process node on X-Axis) (SAME AS PROBLEM-#1)

Problem 3: Qualitative Discussion (short paragraph)

1)How does the delay vs. power dissipation scale as Vdd is lowered? At what point can we stop scaling the supply voltage Vdd? Is there a limit? (HINT: Look at the leakage)

2)Vdd scaling is a great way to reduce power consumption, if the increase in delay can be tolerated. However, what happens to the delay vary between: a) no process mismatch case; b) worst case process mismatch case

3)While energy/computation seems to be reducing with reduced VDD, another important metric is energy/computation * delay (or, energy-delay product). How is Energy-Delay Product scaling? Are we seeing any benefit for low-VDD operation as we continue reducing VDD? Why or why not?

Problem 4: 2-Page Summary Paper

1) Ultralow-voltage, minimum-energy CMOS

2) Sub-threshold Sensor Network Processor

3) Razor-I paper

Read the three papers above, and write a 2-page synopsis, summary of low-voltage, digital logic design. NOTE: I DO READ AND GRADE THESE CAREFULLY, TO DETERMINE COMPLETE UNDERSTANDING OF THIS MATERIAL. PLEASE DO WRITE WELL.