MULTIPLIER DESIGN
The multiplier uses the serial-parallel method of addition to calculate the result of multiplying two 8-bit numbers as shown in figure below. The multiplier receives the two operands A and B and outputs the result C. Operands A and B are loaded in parallel into 8-bit registers and the result C is shifted into a 16-bit register. Multiplication begins on the assertion of a START signal and once the calculation is complete a STOP signal is asserted.
Figure Serial-Parallel Multiplier.
Multiplier Operation
The serial-parallel multiplier is based on the addition of bits in the corresponding column of the multiplication process as shown below. Each column is added in one clock cycle generating the corresponding bit. The resulting bit is then shifted into output register. Therefore the entire multiplication process for the 8 by 8-bit multiplier requires 16 clock cycles to complete the calculation.
a1a0
x b1b0
------
a1b0 a0b0
a1b1 a0b1
------
a1b1 (a1b0 + a0b1) a0b0
The block diagram for the multiplier is shown in figure 2.2 below. The first operand, A, is loaded in parallel and the most significant bit is shifted out during each clock cycle. Operand B is also loaded in parallel and its value is stored in the register for the entire multiplication process. The result C is generated by shifting the added bits of each column one by one into the resultant register. Therefore register RA is a parallel load shift register, RB is a parallel load parallel output register, and RC is a serial input parallel output register.
Figure Multiplier Block Diagram.
In addition to the three mentioned registers, the multiplier also requires 7 one-bit registers to store intermediate values such as the carries generated from each addition, and the bits shifted out from register RA.
Each component to the multiplier is designed and simulated in the following sections.
* It is important to note that all clocked circuits below use an asynchronous active low reset denoted as Resetn, and a clock period of 20 ns.
Multiplier Simulation results
The result of simulating the circuit is shown in figure below.
Figure 8 by 8-Bit Serial-Parallel Multiplier Simulation.
As can be seen, the delay from the START signal to the assertion of STOP is the same as the multiplier controller. The overall multiplier circuit delay is approximately 354 ns. This delay is the result of the fact that the calculation requires 16 clock cycles (320 ns) plus the delay of loading the data (14 ns) and finally the delay to assert the STOP signal (which is one clock cycle after the last shift = 20 ns).
It can be noted that although the critical path of the circuit is
the Xilinx software automatically optimizes the circuit upon running a timing analysis simulation. Therefore, in the optimized circuit, the serial addition of 7 full adders and one flip-flop occurs in less time than the clock period. If the circuit were not optimized a rough approximation for the minimum clock period would be
Tmin = DFFCLKQ + 7 * FA = 14 ns + 7 * 8 ns = 70 ns 14.29 MHz
assuming the AND gate and the setup time for the D flip-flop is negligible.