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The Design of Inverting DC to DC Converters
Before reading this page, please read the introduction.
All of the circuits in this tutorial can be simulated in LTspice®. If you are new to LTspice, please have a look at my LTspice Tutorial
Introduction
There are several ways of generating a negative voltage from a positive one, each with its own merits and drawbacks. This article will discuss the two popular architectures: the single inductor inverter and the Cuk (pronounced Chook) Converter (named after its inventor, Dr. Slobodan Ćuk).
As with all dc/dc converters, each one relies on the flyback properties of an inductor to generate the negative voltage.
(The Cuk converter is a superior solution to the single inductor inverter, but requires 2 inductors which is not desirable in some cases. As the two circuits have different ways of operating, each converter is described in detail, right from the basics, which makes this page rather long. If you want to skip to the Cuk converter, please scroll down and start reading from there)
Simple Inverter
A simple, single inductor based inverter is shown in FIG 1. This circuit converts a 5V input to -5V.
FIG 1
The LTspice circuit of FIG 1 can be downloaded here: Simple Inverting dc/dc converter.
The datasheet of the LT3481 can be downloaded here: LT3481 datasheet.
An internal transistor switches ON connecting Vin to SW, thus applying the input voltage across the inductor L1. The current ramps through the inductor according to the equation
where Vin is the input voltage (and the voltage across the inductor), L is the inductance value in Henries and di/dt is the change in current with time, measured in Amps per second. In the circuit in FIG 1, the above equation becomes
or 1.063 million amps per second. If the internal switch switches off after 1us, the current will have ramped up by 1.063A.
The LTspice simulation shows this current is 1.02 million amps per second. The slight error is due to the voltage drop across the switch causing a voltage slightly less than Vin being applied to the inductor.
When the transistor switches OFF, the inductor tries to maintain its current flow. It does this by generating a voltage across its terminals very similar to a battery, where the current flows from the negative terminal, through the battery, to the positive terminal. Since the right hand side of the inductor is clamped to 0V, the left hand side of the inductor flies negative. The Schottky diode, D1, conducts and clamps the left hand side of the inductor to about 0.3V below Vout and a current circulates clockwise down through the capacitor, up the diode and from left to right through the inductor, thus charging the capacitor. Since the upper terminal of the capacitor is at 0V, the lower terminal charges negatively and a negative voltage appears at the OUT terminal. The internal switch then switches ON again and the process starts over.
The inductor discharges according to the equation
(ignoring the diode drop).
Thus during discharge the change in current with time is also 1.063 million amps per second and this can be seen in LTspice.
It is interesting to note that the value of di/dtis determined ONLY by the inductance value and the voltage across the inductor. The controller IC has nothing to do with setting the inductor ramp current.
The voltage across capacitor C1 is monitored by resistors R1 and R2 and when the junction of R1 and R2 reaches 1.265V (see LT3481 datasheet), the switching stops. Thus by setting R1 and R2 we can determine the final (negative) output voltage at OUT.
It is worth noting that the circuit in FIG 1 is very similar to a buck converter. Indeed the LT3481 is advertised as a buck converter and not an inverter. The only difference is that the node that was the output in the buck converter is now shorted to ground and the node that was 0V (including the ground pin of the controller) is now the negative output. Thus the ground pin of the LT3481 moves down in voltage as the capacitor charges, but the input voltage ground and the output voltage ground are the same node, so it is OK to short them together without things going bang. The input voltage is still referenced to 0V though.
A standard buck converter can be used as an inverter because the phasing of the feedback pin does not change. As the output capacitor charges negatively, the ground reference of the controller (the ground pin) is pulled negative, thus the voltage on all the other pins rise with respect to the ground pin. Thus the junction of R1 and R2 rises as the output capacitor charges – the same as a buck converter.
Compare this with the circuit of FIG 2. This is an alternative solution to the single inductor inverting dc/dc converter. Architecturally this is nearly identical to the circuit in FIG 1.
FIG 2
The input voltage is applied one end of the inductor (with the other end at ground) and the diode conducts on the inductor discharge cycle so the voltage at the OUT pin ramps to a negative voltage. Even the input and output share the same ground. However, here the feedback resistors, R1 and R2, are referenced to the REF pin (which is usually a positive voltage of approximately 1.2V). With 0V on the output, the junction of R1 and R2 is at a positive voltage and ramps negatively (so a standard buck converter cannot be used) as the OUT pin ramps to a negative voltage. R1 and R2 are scaled such that the junction of the resistors is at 0V when the output voltage reaches regulation.
The disadvantage of this architecture is that the REF pin has to source current into the feedback network and this might affect its accuracy, hence the accuracy of the output voltage. The accuracy of the output voltage is also dependent on the accuracy of the feedback resistors. The accuracy of the circuit in FIG 1 is only dependent on the accuracy of the feedback resistors. However, with the circuit in FIG 1, the controller is exposed to a supply voltage equal to the input voltage plus the magnitude of the output voltage, which can be quite high, but this is not normally a problem.
The input current (in green) and inductor current (in blue) for the circuit in FIG 3 are shown below.
FIG 3
It is useful to determine the duty cycle of the converter. This is the ratio of the ON time of the switch to the total switching period.
The inductor charges according to
and discharges according to
(ignoring the diode drop). We are also considering the magnitude of Vout to make the equations easier.
Thus, if the change in charge current is equal to the change in discharge current then
so
where dt1 is the charge time and dt2 is the discharge time of the inductor.
If we define the total switching period (dt1+dt2) as T then the duty cycle (DC) is
Therefore
so
becomes
and from here it can be found that
whereVout is the magnitude of Vout.
Again, the duty cycle is set by the input and output voltages only. The inductor value does not feature in setting the duty cycle, nor does the controller IC. This is true as long as the current in the inductor does not fall to zero. This is called Continuous Conduction Mode (CCM). If the inductor current falls to zero, the duty cycle equation above does not hold and the controller enters Discontinuous Conduction Mode (DCM).
In CCM, if the load current increases, the duty cycle remains unchanged (in steady state). The circuit reacts to the increase in load current by keeping the duty cycle constant, but the midpoint of the inductor current (its dc offset) increases. The switching frequency and the amplitude of the inductor ripple current remain unchanged. In FIG 3, the midpoint of the inductor current is approximately 1.1A and the ripple amplitude is 700mA. If the load increases the midpoint of the current will increase, but the inductor ripple current will still be 700mA and the duty cycle will remain unchanged.
Now, the LT3481 is a buck converter and we have already stated that the circuit in FIG 1 is similar to that of a buck converter. Indeed it has the inductor/diode/capacitor configuration of a buck converter. With a buck converter the average inductor current (equal to the mid point of the inductor current) is also equal to the output current. Since FIG 1 is so similar to a buck converter, it would be convenient to assume that the average inductor current is also equal to the output current for the inverting configuration. However FIG 3 shows the average inductor current as approximately 1.1A when we know that the output current of FIG 1 is 500mA. The inverting configuration has a higher average inductor current because the inductor is actually disconnected from the output while it is charging. Consider a buck converter architecture shown in FIG 4. During the inductor charge phase, current flows through Q1, through the inductor and into the output capacitor. During the discharge phase, current flows up through Q2, through the inductor and into the output capacitor. On both the charge and discharge phase, the capacitor is always receiving current.
FIG 4
With the inverting configuration, shown in FIG 5, on the inductor charge phase, the current flows out of the SW pin through the inductor and down to ground. The output only receives current during the discharge phase. The shorter the duty cycle, the more time the discharge cycle can dump current into the load. Therefore, the average current in the inductor can be represented by
With a load current of 500mA (in FIG 1), and a duty cycle of 50%, the average inductor current will be 1A (assuming no losses).
FIG 5
The single inductor inverter is simple, but due to the higher inductor current and sharp changes in current (see the green waveform in FIG 3), it does not present an elegant way of generating a negative voltage. A more suitable solution (the Cuk converter) will be discussed later.
For completion, below is a design example of a single inductor inverter.
Single Inductor Inverter Design Procedure
Our design brief is to design an inverting controller to convert 12V to -5V at 1A with a switching frequency of 400kHz.
An outline schematic is shown in FIG 6.
FIG 6
The LTC3854 is a standard buck converter, but in FIG 6 is wired as an inverter to give -5V/1A at the OUT terminal.
Inductor Choice
With an input voltage of 12V and an output voltage of -5V, the duty cycle is represented by
The LTC3854 switches at a frequency of 400kHz, so the ON time of the top MOSFET is 29% of 2.5us, or 725ns. A check of the datasheet shows that the minimum ON time of the LTC3854 is 75ns, so we are well within spec.
From
the average inductor current will be 1.41A
The optimal ripple current of the inductor is 40% of the output current. This is a good rule of thumb for most dc/dc converters and represents a trade off between small inductor size and low switching losses. Therefore our design should have an inductor ripple current of 0.56A.
From the equation
during the charge phase the voltage across the inductor is equal to the input voltage, the value of di is 0.56A as calculated above and dt is 725ns. This means our ideal inductor value needs to be 15.53uH. With an average inductor current of 1.41A and a peak to peak inductor current of 0.56A, implies the peak current is 1.69A (and a trough current of 1.13A)
Now, if too much current flows in the inductor, the ferrite that it is wound on saturates with the effect that its inductance rapidly decreases. From the equation above, if the inductance decreases the change in current with time increases, worsening the effect of the over current, so we must ensure that the inductor we choose is rated to handle the current. Thus the saturation rating of the inductor needs to be in excess of the peak current of 1.69A. A saturation rating over 2A should suffice.
Wurth have a 15uH inductor with a saturation current rating of 2.2A
744065150 Datasheet
Rsense Calculation
As the inductor current ramps up it develops a voltage across the current sense resistor R3. The top MOSFET switches off when the voltage across the current sense resistor is 50mV (see LTC3854 datasheet). As stated above, the peak inductor current should be less than 2.2A, so a current sense resistor of 25mOhms ensures the peak current will be less than 2A.
MOSFET Choice - General
In nearly all applications the specification for the top MOSFET is different from that for the bottom MOSFET if maximum efficiency is to be achieved.
Both MOSFETs will be exposed to the difference between the input voltage and the output voltage at some point during the switching cycle, so must both have a drain-source breakdown voltage of at least (Vin + magnitude of Vout). In our design, the input voltage is 12V and the output voltage is -5V, so the minimum breakdown voltage should be 17V. A MOSFET rated with a breakdown voltage of at least 30V should suffice.
The peak current will occur just as the top MOSFET switches off and the bottom MOSFET switches on and the same magnitude of current flows through both devices. Our current sense resistor sets the peak current to 2A, so any MOSFET with a peak current greater than 5A is suitable.
Looking at the block diagram of the LTC3854, we see that the drive circuitry for the bottom MOSFET is powered from INTVCC. The minimum voltage specification on this voltage is 4.8V, so our bottom MOSFET must have a gate turn on voltage of significantly less than 4.8V.
However, the drive to the top MOSFET is powered from INTVCC – 0.3V (the voltage across the flying capacitor) so the turn on voltage of the top MOSFET needs to be significantly less than 4.5V.
In either case, a logic level MOSFET, with a turn on voltage of 1V - 2V is more suitable.
The above parameters represent the bare minimum characteristics of the MOSFETs. However, to get a good design, we must ensure that the losses in the MOSFETs are as low as possible.
MOSFET Choice – Switching and Conduction Losses
The MOSFET switches present 2 losses in the circuit: switching losses and conduction losses.
The switching losses result from current flowing through the MOSFET at the same time that a voltage is across the MOSFET (so power is generated in the MOSFET), during the turn on and turn off times of the MOSFET. For a given gate drive coming out of the controller IC, the lower the Gate-Source capacitance of the MOSFET, the quicker the MOSFET will turn on. Thus the Qg specification of the MOSFET is important and should be as low as possible. The Qg of the MOSFET will also have an impact on the heat dissipation of the chip, especially if the input voltage to the chip is high.
Charge is dictated by the equation:
Charge (Q) = Current (I) x Time (s)
Since Frequency is the inverse of Time, we can write
So we can calculate the current needed to flow into the chip, just to charge the gate capacitance of the FET. Since heat is the product of voltage and current, if the gate charge is high and/or the switching frequency is high, the heat dissipation in the chip will be high.
Once the MOSFET has switched on, the MOSFET presents a small dc resistance between its Drain and Source terminals. This is the MOSFETs ‘Drain Source ON resistance’ or RDSON. Again, this needs to be as low as possible.
Now, MOSFET manufacturers reduce the ON resistance of the MOSFET by constructing many parallel conduction paths between the Drain and Source. Thus, like connecting resistors in parallel, the ON resistance comes down with more parallel paths. However, in connecting Drain Source paths in parallel, a negative effect is that the Gate Source capacitance (Qg) is also connected in parallel, so a low ON resistance (and hence low conduction loss) sometimes implies a high gate source capacitance (hence high switching loss). Thus the MOSFET that is chosen should be a compromise between these two characteristics. In addition, high current MOSFETs tend to come in much larger packages, so meeting the ideals of low ON resistance and low Qg might violate a space requirement spec, so the selection process has to start over. Engineering, as ever, is a compromise.
Indeed looking at the selection tables of the MOSFET manufacturers, it is better to select a MOSFET with a low ON resistance (less than 10mOhms), then filter this selection to remove MOSFETs with a Qg of greater than 10nC, then select a MOSFET from this list, as long as the Gate turn on voltage, Vds and Id can be met. Starting by selecting MOSFETs with a Vds of between 20V and 30V might rule out some higher voltage FETs that are better suited to lower voltage designs. Failing that, download all the results to a spreadsheet and sort from there. I have never had much luck with the parametric searches on MOSFET websites.
Alternatively, download all the MOSFET characteristics into a spreadsheet, remove the ones that don't meet the VDS and ID requirements, then add a column called FOM (Figure of Merit). This column should contain the value RDSON x QG. Then sort by this column and pick the FET with the lowest FOM. This part will be the best compromise between RDSON and QG and ideal for the top MOSFET.
MOSFET Choice – Top MOSFET
The Duty Cycle governs how long the top MOSFET switches on for per period of the switching frequency. We have calculated that the duty cycle is dictated by the ratio of Vout to (Vin+Vout) (when operating in continuous conduction mode). So it can be argued that if the input voltage is high and the output voltage is low (i.e. a low duty cycle), conduction losses in the top MOSFET are not important since the top MOSFET is only ON for a short amount of time. Therefore for low duty cycle circuits, a MOSFET with low Qg should be chosen, almost regardless of RDSON. Although there is no figure as to what constitutes a low duty cycle, any circuit with a duty cycle of less than about 15% warrants having its MOSFET optimised for low Qg with RDSON being largely unimportant.