Device Interface Board Design for Wireless LAN Testing

Project Plan

Team

May 06-15

Client

ECpE Department

Faculty Advisor

Dr. Weber

Team Members

Joseph Chongo, EE

Matthew Dahms, EE

Srisarath (Sunny) Patneedi, CprE

Justine Skibbe, EE

REPORT DISCLAIMER NOTICE

DISCLAIMER: This document was developed as a part of the requirements of an electrical and computer engineering course at Iowa State University, Ames, Iowa.

This document does not constitute a professional engineering design or a professional land surveying document. Although the information is intended to be accurate, the associated students, faculty, and Iowa State University make no claims, promises, or guarantees about the accuracy, completeness, quality, or adequacy of the information. The user of this document shall ensure that any such use does not violate any laws with regard to professional licensing and certification requirements. This use includes any work resulting from this student prepared document that is required to be under the responsible charge of a licensed engineer or surveyor. This document is copyrighted by the students who produced this document and the associated faculty advisors. No part may be reproduced without the written permission of the senior design course coordinator.

Date Submitted

09/22/2005

Table of Contents

List of Figures

List of Tables

List of Definitions

1. Introductory Material

1.1 Abstract

1.2 Acknowledgement

1.3 Problem Statement and Solution

1.3.1 Problem Statement

1.3.2 Problem Solution

1.4 Operational Environment

1.5 Intended User and Intended Use

1.5.1 Intended User

1.5.2 Intended Use

1.6 Assumptions and Limitations

1.6.1 Assumptions

1.6.1.1 User Assumptions

1.6.1.2 System Assumptions

1.6.2 Limitations

1.7 Expected End-Product and Other Deliverables

2. Proposed Approach and Statement of Work

2.1 Expected end product and other deliverables

2.1.1 Functional Requirements

2.1.2 Constraints Considerations

2.1.3 Technology Considerations

2.1.4 Technical Approach Considerations

2.1.5 Testing Requirements Considerations

2.1.6 Security Considerations

2.1.7 Safety Considerations

2.1.8 Intellectual Property Considerations

2.1.9 Commercialization Considerations

2.1.10 Possible Risks and Risk Management

2.1.12 Project Tracking Procedures

2.2 Statement of Work

3. Estimated Resources and Schedules

3.1 Personal Effort Requirements

3.2 Other Resource Requirements

3.3 Financial Requirements

3.4 Project Schedule

4. Closure Materials

4.1 Project Team Information

4.1.1 Client Information

4.1.2 Faculty Advisor Information

4.1.3 Team Members’ Information

4.2 Closing Summary

4.3 References

List of Figures

Figure 1: Teradyne J750 v

Figure 2: Proposed project setup 2

Figure 3: Gantt chart 23

List of Tables

Table 1: Milestone Completion Scoring Rationale9

Table 2: Milestones & Grading Weights11

Table 3: Estimated personal efforts20

Table 4: Estimated additional resources21

Table 5: Estimate project costs21

Table 6: Schedule of Deliverables22

Table 7: Team contact information24

List of Definitions

ESD – Electrostatic discharge, or simply the discharge of static electricity

ECpE – Electrical and Computer Engineering

IG-XL – Software package used to develop test programs for the Teradyne J750

ISU – Iowa State University

I/O – Input and output

PLL – Acronym used for phase locked loop

RF – Radio frequency, refers to signals with frequency in the 9 kHz-300 GHz range

S/R – Refers to a Send/Receive network

Teradyne J750 – Digital input/output test system donated to Iowa State University by Teradyne. See Figure 1.

Figure 1 – Teradyne J750

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1. Introductory Material

Included in the introductory materials are the abstract, acknowledgements, problem statement and solution, operating environment, intended users and uses, limitations and assumptions, expected end-product and other deliverables.

1.1 Abstract

In a previous senior design project, a wireless front-end was added to Iowa State University’s Teradyne J750 high-speed RF tester. This provided the J750 with the capability to wirelessly test digital logic chips. However, one of the unresolved issues is the lack of the ability to pass a clock signal from the J750 to the wireless interface. Currently, the wireless interface is not completely independent and the clock signal is passed via wire to synchronize the two devices.

The goal of this project is to assess the different options of recovering the clock signal at the wireless interface and implement the most viable recovery option. If this is possible, this function will be added to the existing wireless tester. If this were fully implemented, the device would be capable of operating in a completely wireless environment.

1.2 Acknowledgement

The team would like to extend a special thanks to Dr. Robert Weber for the time he has dedicated to advising the team through the course of the project.

1.3 Problem Statement and Solution

This section summarizes the general problem as well as the proposed solution.

1.3.1 Problem Statement

Iowa State University’s Department of Electrical and Computer Engineering introduced a senior design project for the 2004 – 2005 academic year with the goal of developing a wireless interface capable of receiving test signals and transmitting results to the department’s Teradyne Integra J750 tester. Over the span of that year, the May05 team was able to successfully prove that the Teradyne tester is capable of testing digital I/O devices using a wireless S/R network. However, the team’s final design did not include any method for clock recovery and synchronization. Without this, the two devices would not be able to communicate properly and data would be lost. Regardless, the group was still able to test their device by running a clock signal from one device to another via a copper wire.

For this project, the goal is to modify the current setup so that the wireless interface shall be capable of recovering a clock signal transmitted by the Teradyne system. Under current conditions, the Teradyne tester is presented with unknown delay conditions. This is caused by the delay between when the signal is sent to the chip under test and when the chip under test replies. Therefore, this team will develop a method to recover a clock signal at the wireless interface and devise a means for the J750 to receive a reply after some unknown delay. The final system will resemble Figure 2.

Figure 2 – Proposed Project Setup

Graphic courtesy of May05 Senior Design Team

1.3.2 Problem Solution

Currently, the clock used by the wireless interface is connected via wire to the J750. Options must be researched in order to find the feasible solution to make the interface fully wireless. The main option under scrutiny for clock recovery is the phased lock loop (PLL). In the course of research, other more viable options may arise and the best one will be selected based on cost, implementation, user friendliness, and performance.

1.4 Operational Environment

The finished setup should operate indoors with a temperature range of 27°C to 33°C. Because the J750 is sensitive to temperature and the client is the Department of Electrical & Computer Engineering, it will only operate and test digital I/O indoors in an air-conditioned room. Additionally, it should not be subject to mechanical shock or ESD. Mechanical shock should not be an issue as all users are expected to treat the setup with proper care. To ensure that ESD does not become a problem, all users will be expected to wear ESD bands while using the tester.

1.5 Intended User and Intended Use

This section defines the intended users and uses of the project.

1.5.1 Intended User

The intended user is any student or faculty member of the Department of Electrical & Computer Engineering that needs to test the RF capabilities of a wireless device. The user must possess a basic knowledge of RF communication, digital logic and an understanding of how to run tests using the J750. More specifically, the user must be able to synchronize the frequency that runs the clock cycle, with the rest of setup. Additionally, the user must be able to follow the reference manual developed by the previous design team.

1.5.2 Intended Use

The intended use of the project is to sever the tie to all wired inputs from the J750 to the wireless interface. The wireless interface will, therefore, receive a training signal that will program the clock so that it functions on the same cycle as the tester. This preamble will be used for the sole purpose of synchronizing the J750 clock cycle to that of the wireless interface.

1.6 Assumptions and Limitations

The following section defines the expected assumptions and limitations for the end-product. Additional assumptions and limitations will be added as decisions are made about the project.

1.6.1 Assumptions

This section will provide details of the user and system assumptions

1.6.1.1 User Assumptions
  • The user has knowledge in electrical and/or computer engineering.
  • The user knows English. The user-documentation is/will be written in English.
  • The user has previous experience testing circuits with the Teradyne J750.
  • The user has read the Teradyne J750 instruction manual and will observe all necessary safety precautions as prescribed in that manual.
  • The user is knowledgeable of electrical hazards.
1.6.1.2 System Assumptions
  • A sufficient clock training signal can be sent by the Teradyne J750 over the wireless connection to initialize the clock recovery circuitry.
  • The clock recovery circuitry will be able to interact with the existing FPGA.
  • The current wireless communication network can transmit up to five feet. This assumption is based on the May05 team’s documentation.
  • The phase difference between the system clock of the Teradyne J750 and the recovered clock at the wireless interface will not be greater than the overall system clock speed.

1.6.2 Limitations

This section will provide details of the limitations identified with the project

  • The Teradyne J750 is sensitive to temperature fluctuations and must operate within of the calibrated temperature. The current system is set for.
  • The Teradyne J750 is only capable of testing digital I/O. Because of this, all chips tested with the wireless interface must have digital I/O.
  • The maximum rate at which user can send data is at 115.2 Kbps
  • The existing transmitter and receiver communicate at 916.5 MHz. Therefore, nearby wireless signals at similar frequencies may disrupt the setup.
  • The communication link shall be limited to one frequency.
  • The IG-XL software shall be used in writing the test code for the Teradyne J750.
  • The distance between the wireless interface and the Teradyne system will be limited to five feet.

1.7 Expected End-Product and Other Deliverables

This section will provide the details of the expected end-product and other deliverables

By the end of the spring 2006 semester the project will produce:

  • A completely independent electrical interface between the Teradyne J750 and wireless interface for digital I/O chips.
  • The wireless interface will be able to recover a clock signal generated and transmitted by the Teradyne tester.
  • A demo test of a digital chip using the Teradyne J750 and the completed wireless interface.

2. Proposed Approach and Statement of Work

The following section will introduce the proposed approach and state the work necessary for completion of the project.

2.1 Expected End Product and Other Deliverables

The following section will explain the functional requirements and constraint considerations of the end product.

2.1.1 Functional Requirements

The following describes the functional requirements of the end product

  • With the use of a clock recapturing mechanism in connection with the FPGA, the wireless interface will be able to function as an independent entity.
  • The send/receive network must establish a strong communication link between the Teradyne system and the wireless interface.
  • The wireless interface must be capable of testing the I/O of a digital device.
  • The IG-XL software must instruct the Teradyne system to send a preamble for the purpose of clock recovery.

2.1.2 Constraints Considerations

The following will define the constraints considerations of this project

  • The Teradyne J750 is sensitive to temperature fluctuations and must operate within of the calibrated temperature. The current system is set for.
  • The Teradyne J750 is only capable of testing digital I/O. Because of this, all chips tested with the wireless interface must have digital I/O.
  • The maximum rate at which user can send data is at 115.2 Kbps
  • The existing transmitter and receiver communicate at 916.5 MHz. Therefore, nearby wireless signals at similar frequencies may disrupt the setup.
  • The communication link shall be limited to one frequency.
  • The IG-XL software shall be used in writing the test code for the Teradyne J750.
  • The distance between the wireless interface and the Teradyne system will be limited to five feet.
  • Only digital components will be tested with the Teradyne J750.

2.1.3 Technology Considerations

In the following section, technology considerations will be discussed and as well as the method to be used in determining the best action.

Based upon the preference of the faculty advisor, a phase locked loop will most likely be used as the clock recapturing mechanism. The primary technological decision that will be made is the selection of a PLL integrated circuit as a possible means of clock recovery. To determine the most suitable chip, the following criteria will be considered:

  • Cost
  • Chip speed
  • Compatibility with digital I/O
  • Ability to customize with peripheral electronics
  • Reliability

Technological solutions other than the phase locked loop will be considered if complications arise preventing the use of this technology. For example, other solutions shall be considered if a phase locked loop proves to be incompatible with the May05 team’s current setup.

2.1.4 Technical Approach Considerations

The methodologies that will be used in completing this project are described in this section.

The approach to be used will include research, design, implementation and testing. This process will be followed within every stage of the project. This approach will minimize the risks and increase the chances of success.

The first stage is to decide on the goals as well as the budget of the project. The second stage will be to research possible technology, specifically, possible clock recovering mechanisms. For the third stage, the clock recovery circuitry will be designed. Next, parts will be selected and acquired. Following this, the circuit will be built. Lastly, the end-product circuit will be tested.

2.1.5 Testing Requirements Considerations

This section will describe the testing considerations required for the functionality of the phased lock loop.

Testing shall be performed in a modular fashion. The functionality of each stage developed will be verified one stage at a time. The following tests will be conducted to ensure full functionality of the phased lock loop:

  • Test if the existing FPGA interface and Teradyne J750 are still functioning properly.

Criteria for the test are: strong signal and receiving signals as expected.

  • Test the setup by monitoring the signal sent by the Teradyne and the signal received by the interface.
  • Test the setup by monitoring the reply sent by the interface and the signal received by the Teradyne.
  • Test the clock recovery mechanism to ensure the loop bandwidth, phase noise and phase margin are favorable for the setup.

Criteria for the test are: Reliable regeneration of transmitted clock signal.

2.1.6 Security Considerations

This section will discuss the security concerns brought out by the development of the project as well as the operation of it by the user.

This project does not contain proprietary information therefore no concern exists of an outside individual gaining knowledge of this project’s outcome. In the design and test phase of this project, signals to and from the J750 must not violate either FCC regulations or interfere with other nearby devices or laboratory equipment.

2.1.7 Safety Considerations

Safety considerations that include the user as well as the equipment will be described in this section.

The primary concern lies with damaging the equipment. To ensure safety, all users will be required to wear ESD wristbands to avoid unwanted electrical shocks to the J750. As the device will not be operating around high voltage conditions, this is not a concern. In addition to this, the user should use caution when repositioning the Teradyne tester to avoid personal injury.

2.1.8 Intellectual Property Considerations

This project is being implemented for the ECpE department and will not be used for a profit, therefore there are no issues regarding the protection of information. The usefulness of the information, however, will be limited to those who have access to the Teradyne testing laboratory.

2.1.9 Commercialization Considerations

The complete modification to the Teradyne J750, that is, the fully wireless interface, could be useful to companies who test various wireless systems. However, for the initial stage of design, the team will focus only on a single implementation of its design since Iowa State only owns one Teradyne J750 unit. Further commercialization considerations will be investigated only if the project produces a cost effective, user friendly, well performing product.

2.1.10 Possible Risks and Risk Management

The following section summarizes a set of potential risks that may be encountered and the proposed solution(s) to keep the project on schedule.

2.1.10.1 Risk: Failure of components created by previous team.

Management: All team members will observe ESD precautions while handling electronic devices. If an irreparable failure is discovered during testing, all necessary parts will be repurchased and rebuilt based on existing documentation.

2.1.10.2 Risk: Loss of a team member due to internship or coop.

Management: Each team member will document his or her progress in a logbook. Particular attention will be paid to implementation successes and failures so that other team members will not have to retry a solution that has already been proven unsuccessful.

2.1.10.3 Risk: Data or documentation loss.

Management: Each team member shall observe the group established convention for labeling documents with the document author name, date, author and time. Updated documents shall then be emailed to the group. Each team member shall save updated documents as a new file instead of overwriting existing file. Team members will store backup copies on the ISU network. This eliminates the possibility of ever having to start any document from the beginning.