DEVELOPMENT OF VBIC 6-TERMINAL BJT SYMBOL FOR CADENCE SPECTRES SIMULATOR (Modified 03/03)

Siddharth Nashiney

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The Spectre VBIC Model [1]:

Instance Definition

Name c b e [s] [dt] [tl] ModelName parameter=value ...

q  ‘tl’ node is the local temperature

q  ‘dt’ node is the rise above the local temperature caused by the thermal power dissipated by the device being modeled by VBIC.

If the self-heating flag is turned on and ‘dt’ is not given, an internal node is created for self-heating. Hence explicit ‘dt’ and ‘tl’ nodes are not needed for self-heating simulations using the Cadence SpectreS simulator.

The substrate terminal needs to be specified too if ‘dt’ is specified and both substrate and ‘dt’ must be given if ‘tl’ needs to be specified.

Need for explicit external self-heating node

q  To observe temperature plots of the device

q  To model thermal coupling between devices using voltage controlled voltage sources (VCVS).

Creating the VBIC 6-terminal transistor symbol for SpectreS simulations [2]:

q  Copy the NPN to your own library

q  Open the ‘Symbol’ view of the copied NPN cell and add 3 pins ‘dt’, ‘tl’ and ‘S’ .

The direction of the pins would be ‘input-output’ and type ‘square’. Attach the appropriate labels [Add -> label] cdsTerm("dt"), cdsTerm("tl"), cdsTerm(“S”).

Save.

q  Next, go to [Design -> Create Cellview From Pin List] and specify the IO pins ‘C B E S dt tl’, change the view name to ‘spectreS’ and choose the Tool/Data Type to ‘Composer Symbol’. Click OK and then click Modify when prompted.

q  Connect the added 3 pins to the Cellview (spectreS). Save

q  Go to Tools at the icfb window menu and open up CDF. Click edit. Change the CDF type to base. Complete the library and cell name fields. Go to the simulation info field and click edit. Choose simulator to be spectreS. Change the termorder field to ‘ C B E S dt tl ’, netlistProcedure as ansSpectreSDevPrim and prefix as Q.

q  Use this symbol in your schematic to carry out VBIC simulations using spectreS. Connect nodes ‘S’ and ‘tl’ to ground in the schematic.

q  1 volt at the ‘dt’ node = 1 degree rise in temperature

The symbol created is shown in figure 1.

Fig 1: VBIC 6 terminal transistor symbol for SpectreS simulations

REFERENCES

[1] Cadence Documentation, Affirma Spectre Circuit Simulator Reference, Product Version 4.4.6, 2000

[2] http://sourcelink.cadence.com, private communication with Cadence support, July 2002