Design of Low Voltage, LowPower,Wide InputRange Fully CMOS Analog Multiplier
Ali Rezaeia,b Mehdi JafariPanaha,c
aDepartment of Electrical Eng., Tafresh University, Tehran Ave., Tafresh,IRAN
b Corresponding author, Email:
c Email:
Abstract̶ In this paper, afour quadrant voltage modeanalog multiplier, which is an important component in many applications, using CMOS transistors biased in the triode and saturation region is presented. The major improvements of theproposed multiplier are reducing the power consumption, increasing theinput range andincreasing the frequency bandwidth. Thefully CMOS designof the multiplier makes it compatible with digital technology.Simulation resultswith Hspice for 0.18μm CMOS process show thatthis new multiplier structure has very low power consumption, low THD and wide frequency range, which make it suitable for varieties of analog applications.
Keywords: CMOS Multiplier, Low voltage circuits, Low power design, Analog IC design
Introduction
Analog multipliersare the majorbuilding blocks in the signal processing circuits. Multipliers are used in the modulators, PLL’s, AGC’s, detectors, frequency multipliers, neural networks, adaptive filters, fuzzy systems and other applications.
The functionof analog multiplier is that two signalsx and y is applied to the inputs, and the output is a linearproductof these signals,. A0is a constant value and it is called the multiplier gain and the maximum value of A0 is equal toor [1].
The first solid state multiplier was presented by Gilbert [1] and then a variety of multipliers with different characteristicshave been presented [2-7]. Due to advances in digital technology in modern electronics, analog circuits are required to be implemented in the same standard CMOS process for low-cost fabrication.
The multipliers can be implemented in two modes, the voltage mode and the current mode. Each one of these modes can be realizedwith CMOS transistors which arebiased in the saturation, triode orsub-threshold region. In [4]multipliers aredivided into eight categories, depending on the signals application methods, CMOS transistor operation region and thenonlinear cancelation method. In this division, according to the transistor operation region,the input signalscan be applied to drain, source, gate and substrate.Some of categories presentedin this reference are not practical and also some of them have poorlinearity,high power consumption andlow bandwidth, which make them unsuitable for someapplications.In [3] a current modemultiplieris obtained for high speed applications. This structure needs a circuit to produce 2x which should be very precise and increases the number of transistors and power consumption. So itis not suitable for low voltage and low power applications. In [5] a voltage mode multiplier is offered for low voltage applications,in which a common voltage is required forbiasing the transistorsfor the input y. Furthermore, to convert the output current to the voltage, resistor is used which is not suitable for fully CMOS implementation. In [6] a current mode multiplier is presented in which thetransistors operate in weak inversion region.It is proposed for low voltage and low power applications. This structure has very low bandwidth about a few tens of KHz, which is not suitable for high frequency applications.
Achieving a lower level of nonlinear error in CMOS technology is difficultcompared to BJT counterpart because of the different (I-V) relationship of them. Hence, traditional BJT structurescannot be usedeasily for CMOS multipliers. Therefore,various linearization techniques have been used to compensate for the nonlinearity of the square-law device, such as floating gate[10], signal attenuator[11],variableTransconductance[12], using differential pair[5]and using bipolar characteristic of theCMOS transistors[6]. Differential structure, because of common signals cancellation property, is frequently used to cancelthe nonlinear term in the multiplier circuits[1-7].
Multiplier Circuit Analysis
Fig.1 shows theblock diagram of theproposedfour-quadrant multiplier, consistingof single-quadrant multiplier blocks and square-law blocks. In [4], for multiplier implementation, only single-quadrant multiplier or square law multiplier have been used,whereasFig.1 that consist of single-quadrant blocks and square law blocks simultaneously.
According to theblockdiagram shown in Fig. 1, one can write the following relationships:
(1)
(2)Where K is a constant, X and Y are the input signals andV1, V2are theoffset termswhichhave the same values. Thedifferential output signalbecomes:
(3)
Fig. 1 Block diagram of the multiplier
A. Basic circuit
Fig. 2illustrates the basic structure of the purposed multiplier shown schematically in Fig. 1. For implementation of a multiplier using CMOS transistors,it is possible to use in the saturation region and or in the triode region [4]. In thebasic structure of Fig. 2,since CMOS transistors operate in both saturation and triode regions, for multiplier implementation, the combination ofand terms have been used.
Fig.2 Multiplier basic sub-circuit
In this paper, capital letters with capital subscripts are used for DC bias values, and lower case letters with lower subscriptsfor ac signals and capital letters with lower case subscripts for instantaneous valuesare used, respectively.
Having neglected the short channel effect and channel length modulation, thedrain current of CMOS transistor in the triode and saturation region are given withequations (4) and (5), respectively [9].
(4a)
(NMOS) (4b)
(PMOS) (4c)
(5a)
(NMOS) (5b)
(PMOS) (5c)
Where,is thetransconductance parameter,Wis transistor width,Lis transistor length, is carrier mobility, is the gate capacitance per unit area, and is the threshold voltage of the NMOS and PMOStransistors, respectively.
In this circuit, when the input signals are zero,all transistors are in thetriode region and when the non-zero inputs areapplied, transistors M1 andM4are in the saturation region and transistor M2and M3 are in the triode regionorwise versa. Assuming that transistors M1and M4are in the saturation region and transistor M2 and M3 are in the triode region we have:
(6a)
(6b)
(6c)
(6d)
Where is the bias voltage due to the flow ofthe bias current in each transistor, is threshold voltage,x andy are input signals and , are constant DC voltages. In the Fig. 2, the output currents and can be written as:
(7)
(8)
Currents and have the signal components, ,and DC components,, i.e.(). The output current is defined as the difference between and . Using equations (6), (7), (8) and assumeequal KP, yields:
(9)
, will be obtained in equations (10) and (11), respectively.
B. Analysis of the proposed multiplier circuit
The proposed multiplier circuit is shown in Fig. 3. In this circuit, the transistor M1 to M4 form the basic circuit ofFig. 2,transistors M5to M9 are current mirror source which provide the bias currentIB,and M8, M9are in the triode region and transistors M10 to M13are usedas linear resistorswhichconvert the output currents to the output voltages.
Considering equations (6) to (8) for the circuit ofFig. 3, the differential output current is the sameas equation (9).
Fig. 3 Proposed multiplier circuit
According to the circuit ofFig. 3, we have:
(10)
(11)
Since the circuit is perfectly symmetrical and assumingtransistor matching,thenand according to equations (10) and (11), By substituting in equation (9), the DC values are removed and we haveonly the signal values:
(12)
C. Differential activelinear resistance
Using active resistorsinstead of passive resistorscauses fully CMOS implementation of the circuit with lower area occupation on the chip.In the circuitofFig.3,transistors M10to M13are used as linear resistors for converting theoutput current to the voltage. For convenience,this part of the circuit is shown in Fig. 4.
Fig. 4 Differential active linear resistor Circuit
In the circuit shown in Fig.4,all four transistors are in the saturation region. By writing KCL at the output node,,we have:
(13)
Where:
(14)
(15)
By combining equations (13), (14) and (15), the output voltage,, can be found in terms of the output current (),as follows:
Similarly:
Considering equations (16) and (17) and since and ,we have:
From equation (18), the differential output resistorcan be obtained as follows:
By substituting equation (12) into equation (18), the differential output voltage is:
D. Inspection of operationregion of transistors
Since in the proposed multiplier, the wide input range with comparable linearity is obtained by using CMOS transistors biased in the triode and saturation region complementary, careful inspection of operation region of transistors are presented in detail.
a) Transistors M11-M13, M10 - M12
Operationof transistors M11-M13is completely similar to transistors M10 - M12. For proper circuitfunctionality, all four transistors, which are used as active load,must be in the saturation region.Equation (4b) givesthe conditions for NMOS transistors to be in the saturation regions.
According to Fig. 3, the gate-drain voltage ofthe active load transistors are zero and noticing that the threshold voltage of an NMOS is positive, so equation is always established and if equation is achieved the transistors will be in the saturated region.
Equations (21) to (24)can be written, byassumption that transistors M11-M13, M10- M12 operate in the saturation region.
(21)
(22)
(23)
(24)
Considering the DC values, will be equal to and bycombining equations (21) to (24) the gate-source voltages,and ,are obtained as follows:
According to equations (25), (26), regarding to the values of the technology parameters and the bias current, IB, it can be concluded that:
(27)
(28) Hence, transistorsM11-M13, M10- M12 are in the saturation region.
b) Transistors M1, M2, M3 M4
In circuitof Fig 3., when the input signals are zero, transistors M1, M2, M3 and M4 are in the triode region. Since the circuit is symmetrical and assuming matching between transistors,when the non-zero inputs are applied, transistors M1 and M4 are in the saturation region and M2 and M3 are in the triode region or wise versa. Hence, we just obtain the operation region of M1 and M2 for non-zero inputs.
c) Condition of operating M1 in the triode region
In order toM1to be in thetriode region, equation(5c) must be satisfied. According to Fig. 3,the body effect are notcanceled in M1, M2, M3 and M4;, and can be obtained from equation (29)[8].
,where is the threshold voltage when ,isthe body effect coefficient, and is the Fermi potential.
As it can be seen inequation(29), the input y signal affects and hence affects equation (5c).
Using equation (5c)we have:
By combining equations (29) and (30) we obtaine:
Ify has its minimum value, thenwill be maximum and if the equation (31) is satisfied, then M1would be in the triode region.If yis has the maximum value,will be minimum and if the following equation (32) is satisfied, then M1will be in the saturationregion.
(32)
It should be noted that when the gate voltage of M1has the maximum value, the gate voltage of M2isminimum and vice versa. Therefore, it can be concluded that when M1operates in the saturation region, M2 is in thetriode region and when M1operates in the triode regionM2 is in the saturation region. There arethe same conditions for M3and M4. Hence, according to the input signals, when M1 and M4 are in the triode region, M2 and M3 are in the saturationregionand vice versa. In all cases, equation (12) represents the multiplication of two signals.
E. Input Range
If xand yhave their maximum values, according tothe equation (32), M1and M4 will be in the saturationregion and saturation of the transistors determines the maximum input range.
We have:
(33)
According to equation (4a)VGS of the transistors M1, M2, M3 and M4in saturation region can be obtained as follows.
Substituting equation (34) into equation (33) and assuming that both inputsx, yhaveequalswings, then we have:
As it can be seen from equation (35), the maximum input range dependsonIBand the technology parameters.
F.Power Consumption
Since PMOS transistorsneed lower drain current in comparison with NMOS transistors,they are good choicesfor input stageoperatedin thesaturation or triode regionsin order todecrease the power consumption [2]. In [2, 5, 6, 7], transistors biasingrequires extra circuitswhich causesan increase in the power consumption, but in the proposed multiplier circuit,for biasing,only the current source have been used that is one of major reasons to reduce the power consumption.
The power consumption forthe circuit ofFig.3 is:
(36)
Where, is supply voltage, is the value of the current sourceand is the voltage across this current source,is the total current and can be obtained as follows:
(37)
In the circuit of Fig.3, we have:
(38)
According to equations(36) to (40), the power consumption is obtained as follows:
It should be noted from equation (41) thatincreasing IB will increase the power consumption.
G. Frequency Response
Although the precise calculation of frequency responses is most often left to computer simulations, there is much insight that can be obtained by finding the dominant frequency effects in integrated circuits [9]. In the presented circuit ofFig. 3,because of thesimple method of applying theinput signals (the inputs are applied to the gate and source directly) and considering short channel length for the transistors, the proposedmultiplier has relativelyhigh cut of frequency. The active resistors used in Fig. 3 have themaximum effect on the frequency response characteristic. For eachone of the outputs, the dominant pole frequency can be
considered as follows:
For the output node,, we have:
According to equations (42) and (43):
The dominant pole frequency of is actually equal to that of . Since small areatransistors are used, the gate-source capacitors are small andhence according to (44) it is expected that thecut-off frequency will be large.
Simulation Results
The designed multiplier circuit of Fig. 3 was simulated using Hspice for 0.18µm CMOS process with main parameters of ,, IB=5µAand .
Transistorssizes are shownin Tab. 1; these sizesare selected in order to optimize power consumption, input range and bandwidth.
In section 3, the analysis of the maximum input range has been done. According to (35), the maximum input range is a function of the bias current,IB,and this current has selectedregarding to the trade-offs between the maximum input range, power consumption and bandwidth.
(Fig. 5a) shows simulated DC transfer characteristics of theproposed multiplier, when x was swept continuously from-0.3v to 0.3v while y was varied from -0.3v to 0.3vwith 0.1v step size. It can be seen that the maximuminput range is %50 of the power supply voltage and the multiplier is four quadrants. Since in the proposed multiplier circuit of Fig.3, and , simulation resultvalidates the theoretical calculations offeredin (35).The derivative of the transfer characteristic is show in (Fig. 5b)whichillustrates the error performances of the DC transfer characteristic. In section 4,the analysis of thepower consumptionhas been carried out which resulted toequation (41).Simulation results shows a power consumption about 33µw, which is in agreement with the theoretical calculations.
(a) (b)
Fig. 5 (a)DC transfer characteristic(b) Error performances of the DC characteristic
In order to demonstrate theapplication of the proposed multiplier in a modulator circuit, transient response simulation for the input signals is shown in (Fig.6a). To illustrate the nonlinearity characteristics of the modulator circuit, the frequency spectrum of the output waveform is shown in (Fig. 6b).
(a) (b)
Fig. 6 (a) Output transient responses (b) Frequency spectrum of the waveform in Fig. 6
Frequency response simulation resultof the proposed circuit is shown in Fig. 7with the inputsignal. As it can be seen, the circuit has highbandwidth of whichmakes the circuit suitable for high frequency applications.
By increasing the amplitude of the input signals,the non-linear effects of the CMOS transistors will be increased. This causes an increase in the THD and non-linear effect in the DC characteristic. There is a direct relationship between the THD and the multiplier circuit linearity, when and are applied to the inputs, the THD is equal to 0.69% and for inputs and , the THD of 0.74% is achieved. Fig.8 shows the THD values for various DC inputs x and y
Fig. 7 Frequency response of the proposed multiplier
Fig. 8 THD as a function of the input signal x & y
Tab.2, represents a performance comparison between the proposed circuit with references [2, 5,7]; which shows that the proposed multiplier has better characteristics.
Conclusion
A four quadrant analog multiplier circuit using CMOS transistors biased in the triode and saturation region is designed and simulated.The proposed multiplier offers reduced power consumption, increased input range and increased bandwidth, which makes it suitable for high frequency, low power applications. The fully CMOS design of the multiplier is an advantage for low cost implementation using standard digital CMOS technology. The proposed circuit has been simulated with Hspicefor 0.18μm CMOS process. The power supply voltage of circuit is 1.2v.The simulation results shown that the THD is less than 0.74% for input frequency of 100KHz, -3dB bandwidth is 3.7GHz and the power consumption is about 33μw.
References
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