EE 280
Design of Logic Circuits
Course Syllabus
Summer 8-Wk, 2003
(June 12, 2003 – August 7, 2003)
Instructor:Dr. J. Robert Heath
Office:475 Anderson Hall ((859) 257-3124)
Email:
Web Page:
Office Hours:M (11:30 a.m. - 12:30 p.m.)
Th (9:00 a.m. - 10:00 a.m.)
Text:1. Stephen Brown and Zvonko Vranesic, FUNDAMENTALS OF DIGITAL LOGIC WITH VERILOG DESIGN, McGraw-Hill, 2003 (Required).
2. Michael D. Ciletti, Modeling, Synthesis, and Rapid Prototyping with the Verilog HDL, Prentice Hall, 1999 (Optional – On Reserve in
Library).
3. Simucad Inc. Silos III Users Manual, (Optional – On Reserve in CE Microlab).
Meeting Schedule:MTWThF (10:20 a.m. - 11:20 a.m.) AH 257
Course Objectives:The study of number/arithmetic systems and Boolean algebra; modeling, analysis, design, and synthesis/implementation of combinational logic circuits; modeling, analysis, and design of flip-flop memory elements; modeling, analysis, design and synthesis/implementation of synchronous and asynchronous sequential logic circuits; logic design problems using SSI/MSI/LSI TTL integrated circuits and CPLD/FPGA integrated circuits; and design capture, simulation, and design verification of digital circuits via use of a Hardware Description Language (HDL) and modern CAD software. (Prereq: CS 115).
Topical Outline:I. Electrical and Electronic Systems
A. Continuous (Analog) Systems
B. Discrete (Digital) Systems
C. Digital System Modeling, Design Capture, and Design
Validation/Verification via Pre-Synthesis Simulation Using Hardware Description Languages (HDLs)
- Synthesis, Implementation, and Post-
Synthesis/Implementation Simulation for Design
Validation/Verification
II.Number/Arithmetic Systems
A. Notation
1. Juxtapositional
2. Polynomial
B. Signed-Magnitude Numbers
C. Fixed Pt. Numbers
D. Floating Pt. Numbers
E. Binary Arithmetic Operations
F. Number/Base Conversions
G. Complementary Arithmetic
1. Radix Complement
2. Diminished Radix Complement
III. Computer Codes
IV.Boolean Algebra and Logic Gates
A. Postulates
B. Theorems
C. Duality
D. Boolean Functions
E. Truth Tables
F. Logic Gates
G. Implementation of Logic Functions
H. Design Capture via the Verilog Hardware Description
Language
I. Design Validation/Verification via Pre- and Post-Synthesis
HDL (Verilog) Simulation
V.Minimization of Logic Functions
A. Algebraic
B. Karnough Maps
C. Quine-McCluskey
VI.Design of Combinational Logic Circuits (Systems)
A. Circuit Specifications
B. I/O Identification
C. Circuit Truth Table
D. Circuit Functional Equation(s) Development
E. Equation Minimization
F. Implementation of Functional Equation(s)
G. Combinational Hazards
H. Design, Design Capture, and Design Verification
Via Pre- and Post-Synthesis Simulation Examples
VII. Integrated Circuits
A. Levels of Integration
B. Logic Families and Characteristics
C. Digital Design Capture, Simulation/Analysis, and
Synthesis CAD Software
VIII.MSI/LSI/VLSI Level Implementation of Logic
Functions
A. Multiplexers
B. Decoders
C. ROMS
D. PLA's, PAL's, CPLD's and FPGA's
IX.Sequential Logic Circuits
A. General Model
B. State Diagrams
C. State Tables
D. Flip-Flops
X.Design of Synchronous Sequential Logic Circuits
A. Equivalent States
B. State Diagram/Table Reduction
C. State Assignment
D. Excitation Tables
E. Design Algorithm
F. Incompletely Specified Circuits
G. Design, Design Capture, and Design Verification
Examples via Use of a HDL and HDL Simulator
XI.Design of Pulse-Mode Asynchronous Sequential Circuits
A. Pulse Mode Model
B. Design Algorithm
C. Design, Design Capture, and Design Verification
Examples via Use of a HDL and HDL Simulator
XII.Design of Fundamental Mode Asynchronous Circuits
A. Fundamental Mode Model
B. Analysis of Level Sequential Circuits
C. Flow Table Generation
D. Cycles and Races
E. Fundamental Mode Output Maps
F. Design Examples
Homework:Homework will be assigned daily. You will be provided solutions to
all homework problems. You must work “all” homework problems to do well in this course.
Design and Design
Verification Projs:During the term you will design several logic circuits, capture
each design using a HDL (Verilog), and verify correct design and
functional/timing operation of each logic circuit via use of Simucad's
SILOS III Verilog pre-synthesis sumulation CAD tools or another appropriate CAD tool set. We may synthesize some of our designs to Field Programmable Gate Array (FPGA) technology chips using appropriate Simulation and Synthesis/Implementation CAD Software.
Outcomes:Upon completion of this course students should demonstrate an
ability to:
1. Perform arithmetic in various number/base systems.
2. Apply Boolean Algebra to modeling, design, analysis, and minimization of logic circuits.
- Design combinational logic circuits and use HDL simulation
CAD tools to verify correct design and operation of the circuits.
4. Design synchronous and asynchronous sequential logic circuits
and use HDL simulation CAD tools to verify correct design and
operation of the circuits.
5. Apply timing analysis to design a reliable logic circuit when
multiple signal paths are involved.
Grade:1. Three (3) Tests: (June 27, July 15, and July 31) - 60%
2. Design and HDL Design Verification Projects -20%
3. Comprehensive Final Examination (August 7)-20%
Your final grade will be determined by the number of points you
have accumulated from 100 possible as follows: A: 90 - 100 pts.
B:80 - 89 pts.
C:70 - 79 pts.
D:60 - 69 pts.
E: < - 60 pts.
Make-up
Examinations:Make-up examinations will only be given to students who miss
examinations as a result of excused absences according to applicable
current university policy. Make-up examinations may be in a different format from a regular examination and may include oral examinations.
University Studies
Program:This course is part of the University Studies Program, which is
designed to provide a comprehensive liberal arts education to all
undergraduates. The course PHI 320, Symbolic Logic I, can be paired
with this course to fulfill a portion of the cross-disciplinary
requirement in University Studies.
Class Attendance:Attendance of all class lectures is required to assure maximum course
performance. You are responsible for all business conducted within a
class.
Cheating:Cheating will not be allowed or tolerated. Anyone caught cheating
will be dealt with according to applicable University policy.
(Assignment of a grade of E for the course).
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