Abstract

The sigma-delta modulator based closed loop systems make high resolution, high SNR, low frequency systems. The sigma-delta analog to digital converter consists of the modulator followed by the decimation filter. In this project the design of decimation filter, which performs the role of filtering the shaped quantization noise and converting 1-bit data stream into 20 bit high-resolution output is reported.

An efficient multi-stage decimation methodology is adapted where decimation is performed in several stages due to high order of the decimation filter which is almost impossible to implement in hardware. The multi-stage structure consists of Cascaded Integrator Comb (CIC) filter followed by FIR. The specifications of decimation filter are derived from the specifications of a third-order single bit sigma-delta modulator. Use of cascaded integrated comb filter for the first stage has made the implementation easy by requiring no multiplication. Furthermore, it can be used to decimate the data by a large factor, allowing easier implementation of the following stages. Distributed arithmetic algorithm is used to design FIR filters. Software model for the decimation filter is developed using MATLAB /Simulink, and integrated with sigma-delta modulator model to analyze the responses. The hardware model for the filter is developed using Verilog HDL.

The design is implemented and tested using SPARTAN 3E FPGA. Filter has got passband of 100Hz and stopband of 200Hz .The test environment has the feature of taking external input as well as the internally stored bit stream in LUT. The designed system exhibits good linearity and the design consumes a power of 40.4mW.

Table of Contents

Title Page………………………..…………………………………….………….....…..i

Certificate……………………………………………………………………………….ii

Acknowledgement...... iii

Abstractv

Table of Contentsv

List of Tablesi

List of Figures

Nomenclature

Abbreviations

1 – Introduction

1.1 Introduction to sigma-delta data converters

1.2 Overview of over-sampling and decimation

1.3 Application of sigma-delta data converter

1.4 Advantages and disadvantages

1.5 Summary

2 – Literature Review...... !Unexpected End of Formula

2.1 Introduction

2.2 Literature review on decimation filter and distributed arithmetic

2.2.1 Understanding of cascaded integrator-comb filter

2.2.2 Understanding of finite impulse response filter

2.2.3 Understanding of distributed arithmetic......

2.2.4 FIR Filter with large number of coefficients......

2.2.5 Signed distributed arithmetic example......

2.2.6 Journals/transactions referred......

2.3 Summary of literature review......

2.4 Design specification and block diagram......

2.5 Fist stage cascaded comb filter......

2.6 FIR filtering......

2.7 Summary......

3 – Problem Definition......

3.1 Problem definition......

3.3 Problem statement......

3.3 Project objectives......

3.4 Methodology adopted to meet the objectives......

4-Software Reference Modelling of Decimation FIR Filter......

4.1 Introduction......

4.2 Construction of software reference model......

4.2.1 Design of cascaded integrator-comb filter......

4.2.2 Design of FIR filter......

4.2.3 Simulink model of sigma-delta data converter......

4.3 Summary......

5 – Conclusions and Recommendations for future work......

5.1Conclusion......

5.2Recommendationsfor further work......

References......

Appendix A: Snapshot of Verilog HDL design source files and libraries......

List of Tables

Table 2.1: Distributed arithmetic table......

Table 2.2: Distributed arithmetic calculation......

Table 2.3: Literature review a table summary......

Table 2.4: Specification of sigma-delta data converter......

Table 2.5: Over all characteristics of the decimation filter......

Table 2.6: Cascaded integrator comb filter......

Table 2.7: Requirements of FIR filtering......

Table 4.1: CIC filter step response......

Table 4.2: Specification of FIR filter......

Table 4.3: FIR1 MATLAB and scaled coefficients......

Table 4.4: FIR1 MATLAB scaled coefficients step response......

List of Figures

Nomenclature

Symbol UnitDescription

MHz106 Hertz Frequency

KHz103 Hertz Frequency

mA10-3 AmpereCurrent

VvVoltage

 A 10-6Ampere Micron

mW10-3WattsPower

W10-6WattsPower

nW10-9WattsPower

ssSecond

ns10-9 secondsSecond

ms10-3 secondsSecond

Abbreviations

ADC -Analog to Digital Converter

ASIC-Application Specific Integrated Circuit

BIST-Built In Self Test

CIC-Cascaded-integrated comb

CMOS-Complimentary Metal Oxide Semiconductor

CSD-Canonic sign digit

DA-Distributed Arithmetic

DAC-Digital to analog converter

DSP-Digital signal processing

FIR -Finite Impulse Response

FPGA-Field Programmable Gate Array

HDL-Hardware Description Language

ISE-Integrated Software Environment

IC-Integrated circuit

LUT-Look Up Table

MSB-Most Significant Bit

MEMS -Micro Electro Mechanical Systems

NTF-Noise Transfer Function

OSR-Over Sampling Ratio

SNR-Signal to Noise Ratio

STD-Standard

VLSI-Very Large Scale Integration

1

1 – Introduction

The performance of digital signal processing and communication systems is generally limited by the precision of the digital input signal, which is achieved at the interface between analog and digital information. As the speed and capability of the DSP cores increases, must the speed and accuracy of the converters associated with them also should increase. Sigma-Delta modulation based analog-to digital conversion technology is a cost effective alternative for high-resolution converters (more than 12 bits), which can be ultimately integrated on digital signal processor ICs.

1.1 Introduction to sigma-delta data converters

The basic concepts of Delta modulators and Sigma-delta converters are the use of feedback for improving the effective resolution of a quantizer. The concept came up in 1954 and the patent was granted in 1960 to cutler. His system was based on generating and subtracting from the input signal the quantization error of the low-resolution quantizer placed in the forward path of a feedback loop. In 1962, it was proposed by the Inose yasuda and Murakami to add the loop filter to front end of the delta modulator and then move it inside the loop. For a Simple case of the integrator used as a loop filter, the resulting system contained an integrator in the forward path, followed by the 1-bit quantizer and the feedback loop contained only a 1-bit digital to analog converter (DAC). Since the system contained a delta modulator and the integrator, they named it as delta-sigma modulator, where sigma denoted summation performed by the integrator. It was often called Sigma-Delta modulator by later works. Today both names are in use. The output of the modulator contains the original input signal plus the first difference of the quantization error, as was the cause of the error feedback coder. Thus the both delta-sigma and error feedback coder are the noise shaping modulator. They suppress the error in the base band and thus achieve improved dynamic range across baseband independent of the signal frequency [1].

The sigma delta converters did not gain importance until the development of digital VLSI technology, which provides the practical means to implement the large digital signal processing circuitry. VLSI has helped to implement both analog and digital circuitry in one die .Since the sigma delta ADC are based on digital filtering techniques, almost 90% of the die is implemented in digital circuitry. The additional advantage of such approach is higher reliability, increased functionality and reduced chip cost [2].

Conventional high-resolution analog to digital converters, such as successive approximation and flash type converters, operating at the Nyquist rate (sampling frequency approximately equal to twice the maximum frequency in the input signal), often do not make use of high speeds achieved with a scaled VLSI technology. These Nyquist samplers require a complicated analog low pass filter (often called an anti-aliasing filter) to limit the maximum frequency input to the analog to digital converters, where as sigma-delta converters use a low resolution analog to digital converter (1-bit quantizer), noise shaping, and a very high over-sampling rate. The high resolution of the Sigma-Delta converters is achieved with help of decimation (sample rate reduction) filters, which are also called digital filters [2].

An Inertial Navigation System use motion sensors like accelerometer to continuously calculate the position and velocity of a moving object without the need for external references. Inertial-navigation systems are used in many different moving objects, including vehicles, aircraft, submarines, spacecraft, and guided missiles. In all these applications accelerometer measures changes in a differential capacitancewhich result from acceleration input(change in capacitance is directly proportional to acceleration and MEMS sensor output is directly proportional to change in capacitance). This capacitance is converted in to voltage using readout electronics (continuous-time capacitance to voltage converter) which is made up of op-amp based design and feed to 3rd order sigma-delta modulator whose one bit output is used for forced feedback. The digital section of the data converter is used to convert 1-bit data stream into 20 bit data which is given to Inertial Navigation System as sensor output. This project reports about design of Digital section of sigma-delta data converter.The block diagram of a Simple sigma-delta converter with accelerometer application is shown in Figure 1.1. The MEMS sensor has got bandwidth of 100Hz. Because this the system which is following the sensor electronics (modulator) should have the band width of 100Hz and has the feature of shaping the frequencies above the bandwidth(noise shaping).

Figure 1.1: Block diagram of sigma-delta data converters with accelerometer application

All the specification required for the decimation filter is derived from the specification of sigma-delta modulator as well as from the requirement of inertial navigation system. The 20bit digital output from the decimation filter is given to computer of inertial navigational system which computes it’s on updated position by integrating information received from the motion sensors.

1.2 Overview of over-sampling and decimation

An over-sampling converter uses an over-sampling rate of Fs =N*Fs followed by a digital-domain decimation process to compute a more precise estimate for the analog input at the lower output sampling rate (Fs), which is the same as used by the Nyquist samplers. Regardless of the quantization process, over-sampling has immediate benefits for the anti-aliasing filter. Over-sampling in converters prevents the filters from having steep transition band, which will help for implementation of the filter. The decimation process can be used to provide increased resolution [2].

1.3 Application of sigma-delta data converter

The largest application of the delta-sigma conversion is in the field of digital telephony. Digital cellular telephones utilize delta-sigma both for voice band speech coding and for IF-to-base band radio interface data conversion, such as quadrature and in-phase modulation /demodulation. One thing that takes the full advantages of the inherent qualities of delta-sigma conversion is digital audio. Few of the other application of sigma-delta modulator are listed below.

Accelerometer

Pressure measurement

Weigh scales

Thermocouple Measurements

Thermistor Measurements

Portable instrumentation

Sensor measurement

Temperature measurement

This particular project is aimed at Accelerometer application, which requires measuring 1µg in 1g range (1µg resolution in 1g range). To meet this particular specification it is necessary to design a sigma-delta data converter which has 120dB SNR. So decimation filter is also designed with the specification of 120dB attenuation in the stop-band and with a minimum ripple of 0.0005 dB in pass-band

1.4 Advantages and disadvantages

High resolution above 12 bit can be achieved

Without CMOS the digital Decimation and filtering is too expensive

1.5 Summary

Sigma-Delta data converters are used to get high resolution (greater than 12 bits) digital outputs which can be ultimately integrated on digital signal processor ICs. The purpose of the modulator is to remove the noise from base band and to perform noise shaping. Filtering noise which is aliased back in to base-band is the main function of the digital filtering stage and its secondary function is to convert 1-bit data stream that has a high sample rate and transform it in to a 20 bit data stream at lower sample rate.

This documentation is organized with a total of 6 chapters. Chapter 1 gives a brief introduction to Sigma-delta data converter and its application. Chapter 2 gives the literature review carried on decimation filter and distributed arithmetic algorithm for project. Chapter 3 contains the problem definition, objectives and methodologies adapted to accomplish the set of objectives. Chapter 4 describes about the software (MATLAB) modelling of the decimation filter and simulation results. Chapter 5 describes about the hardware modelling and testing of decimation filter in FPGA. Chapter 6 gives the conclusion and future work that can to be carried out in decimation filter.

2 – Literature Review

2.1 Introduction

The decimation and filtering can be performed using different architectures, but it is very much important to know which is the best one and can be implemented in hardware using less resources. It is believed that the best architecture is the one which can be accommodated in hardware consuming less area and power.

2.2 Literature review on decimation filter and distributed arithmetic

Practically it is not possible to implement a single filterthat would meet the characteristic of decimation filter, because order of such filters would be close to5000.It is impossible to implement such filters in hardware. So it is necessary to split the architecture of decimation filter in to two parts [3], CIC filter followed by FIR stage as shown Figure 2.1.

Figure 2.1: Architecture of decimation filter

The output of sigma-delta modulator is at the rate of 62.5 KHz and because of this reason first stage of decimation filter (CIC) reads the input at the rate 62.5 KHz and performs a decimation of 25 and obtains an intermediate frequency of 2500Hz. The decimation factor of CIC filter is selected 25 based on following factors

Droop in the frequency response of the filter at the edge of the signal band

Order of the FIR stages that follows the CIC filter

Based on the intermediate frequency and order of the filter, decimation factor for the stage FIR filter is fixed to 4 and the output sampling frequency of the filter is 625Hz. Since the resonance frequency of the inertial navigation system is 1 KHz. Because of this reason output of the decimation FIR filter will be at the rate of 625Hz. The FIR filters are operation with a clock frequency of 2 MHz so that the filter finishes it’s computation before the arrival of next input.

2.2.1 Understanding of cascaded integrator-comb filter

Cascaded integrator-comb (CIC) digital filters were introduced to the signal-processing community, by Eugene Hogenauer [4], and mainly used in efficient implementation of decimation and interpolation. Bonus in using CIC filters, and a characteristic that makes them popular in hardware devices, is that they require no multiplication. The arithmetic needed to implement these digital filters is strictly additions and subtractions only. CIC filters are known in the field of electronics with different names, like moving average filter or recursive filter.

The two basic building blocks of a CIC filter are integrator and comb. An integrator is just a single pole IIR filter with a unity feedback coefficient. This system is also called as accumulator.

For decimators, the gain G at the output of the final comb section is

G = (RM)N ------(1)

Where R is rate of change and M is differential delay

Assuming two’s component arithmetic, the gain G is used to calculate the number of bits required for the last comb due to bit growth. If Bin is the number of input bits, then the number of output bits, Bout is

Bit growth (Max) = [Nlog2RM+Bin] ------(2)

N = Number of stages

COMB Delay = M

Input word length = Bin

R = Decimation factor

It is also the bit width required for each stage of integrator and comb.

Hardware implementation of Cascaded integrator-comb filter

Decimation to a lower sampling rate is achieved by taking one sample out of every ‘D’ sample.

Figure 2.2: Architecture of single CIC filter [4]

The Figure 2.2 shows the hardware implementation architecture for single stage CIC filter, as the number of stages increases number of integrator and the comb section also increases.

The order of the decimation filter is fixed to six because it has to be one more that the order of the 3rd order sigma-delta modulator plus the 2nd order MEMS sensor. When CIC filter is build six integrator section is cascaded together with six comb section and for the hardware reduction it is better to have decimation section between integrator and comb section.

2.2.2 Understanding of finite impulse response filter

Finite Impulse Response (FIR) Filter is one of the primary types of filters used in digital signal processing application. Since the filter does not use feedback the impulse response of the filter is finite.

Some of the advantages of FIR filter are listed below [5]

They are suited to multi-rate application

Easily designed to be linear phase

Simple to implement in hardware

The three most important popular method used for designing FIR filter are Parks-McClellan method, widowing and direct calculation [5].

Parks-McClellan: - it is most widely used FIR filter design method. It is an iteration algorithm that accepts filter specifications in terms of passband and stopband frequencies. We can specify all the important filter parameters in this method, this made this technique popular. Two stage FIR filters for the decimation filters are also designed using this algorithm.

Windowing: -In the windowing method, an initial impulse response is derived by taking the Inverse Discrete Fourier Transform of the desired frequency response. Then, the impulse response is refined by applying a data window to it.

Direct Calculation: - The impulse response for the certain type of filters can be calculated directly from formulas.

Figure 2.3: Conventional tapped delay line FIR filter [5]

Figure 2.3 shows the conventional tapped delay line realization of this inner product calculation. Even though diagram gives us an idea about the mechanism of FIR filter actual FPGA implementation cannot be realized from this. Two most common way of implementing FIR filter in hardware are