1. Deriving a state table from a state diagram.

The state diagram of a sequential circuit is shown in the figure below. Complete the corresponding state table. The Q1 state bit is implemented using a positive edge-triggered JK flip-flop and the Q0 bit is implemented using a positive edge-triggered D flip-flop. For your convenience, the characteristic tables of JK and D flip-flops are attached. Use the state encoding 0 = 00, 1=01, 2=10, and 3=11.

D / Q(t+1) / Operation
0 / 0 / Reset
1 / 1 / Set
J / K / Q(t+1) / Operation
0 / 0 / Q(t) / No change
0 / 1 / 0 / Reset
1 / 0 / 1 / Set
1 / 1 / Q’(t) / Complement

PresentState / Input / NextState / Output / Flip-flop Inputs
Q1 / Q0 / X / Q1 / Q0 / Z / J1 / K1 / D0
  1. Derive an Excitation Table

A Greg-Paul flip-flop has two inputs G and P and one output Q. Its characteristic table is shown below. Complete the excitation table for this flip-flop.

G / P / Q(t+1)
0 / 0 / 0
0 / 1 / Q(t)
1 / 0 / Q’(t)
1 / 1 / 1

Excitation Table:

Q(t) / Q(t+1) / G / P
0 / 0
0 / 1
1 / 0
1 / 1
  1. Hazards
  1. Is it possible to have a static-0 hazard in this circuit? If yes, identify a single input change that may cause a static-0 hazard?
  1. Is it possible to have a static-1 hazard in this circuit? If yes, identify a single

input change that may cause a static-1 hazard?

  1. Is it possible to have a 0-functional hazard in this circuit? If yes, identity a two

input change that may cause a 0-functional hazard?

  1. Is it possible to have a 1-functional hazard in this circuit? If yes, identify a two

input change that may cause a 1-functional hazard?

  1. What changes should be made to this circuit to eliminate all possible static

hazards? Express your answer as a Boolean expression.

  1. Even More Hazards!!

  1. On the diagram above, plot the waveforms for "b", "c", and "F".
  1. Circle the type of hazard that the circuit will have (CIRCLE ALL THAT ARE TRUE)

Static Zero Static One Functional/ Dynamic

Hazard Hazard MICS Hazard

Hazard

  1. A Boolean function f(A, B, C, D) is implemented in SOP format as follows:

Identify ALL the product terms that need to be added to this SOP expression to guarantee that it is free of all the static and dynamic hazards.

Answer:

  1. Shift Register Design

  1. Counters

CTR4 is the four bit up-counter with parallel load. CO is carry out and is not needed for this problem. Use as few as possible AND, OR, NOT logic gates and a single CTR4 counter to realize the following count sequence:

1, 2, 3, 4, 7, 8, 9, 10

After counting to 10, it will start from 1 again. Use "1" to indicate logic 1, and "0" to indicate logic 0 wherever needed in your implementation.

  1. Designing with counters

Design a synchronous BCD counter with parallel load using a 4-bit binary counter

with parallel load, 2-to-1 multiplexors, and some logic gates. The BCD counter has

one LD input, four data inputs D3, D2, D1, and D0. When LD is high, the counter is

initialized to the values in the D3, D2, D1, and D0 inputs. When LD is low, the

counter counts up 0, 1, …, 9, 0, 1, …. If the counter is loaded with an unwanted state

(i.e.,10, 11, 12, 13, 14, and 15), the next state should be 0. All operations take place at

the rising edge of CLK.

  1. Buses and Register Transfer

Two different register transfer structures are shown below:


9. Verilog (see also quiz 3 review – problem 11 for another Verilog problem)

10. Designing a state diagram from a word description

Draw a state diagram for a Mealy machine that does the following. It has one input X

and one output Z. The output Z is 1 only when the number of 1s received at the input

is an ODD multiple of 3 (i.e., 0, 3, 9, 15, 21,…). Designs with too many states will

be penalized.

11. Designing a state diagram from a word description