DDR-PHY interoperability using DFI
The DDR PHY Interface (DFI) is an interface protocol that defines the signals, timing parameters, and programmable parameters required to transfer control information and data over the DFI, to and from the DRAM devices, and between the MC and the PHY.
DFI applies to: DDR4, DDR3, DDR2, DDR1, LPDDR4, LPDDR3, LPDDR2 and LPDDR1 DRAMs.
Why is DFI required ?
The DFI interface is not necessary when the MC and PHY are being developed specifically to work together. However, in many situations, the MC and PHY are designed separately - often by different companies. DFI permits companies to develop both MC and PHY IP designs knowing that they will be able to interoperate with the devices developed by other companies.
Additionally, MC devices are primarily clock-based, where the PHY generally consists of a significant amount of analog logic, therefore, the two devices are often developed by different engineers even within the same company; DFI creates a well-defined interface for these groups to work with.
Block Diagram showing DFI usage
DFI specifications are developed & maintained by Workgroup made up of leading companies, including : ARM, Cadence, Intel, LSI, Samsung, ST, Synopsys.
Official webpage for all DFI-related information, announcements & knowledge materials is :
Frequency Ratios Across the DFI
In a DDR memory subsystem, it may be advantageous to operate the PHY at a higher frequency than the MC. If the PHY operates at a multiple of the MC frequency, the PHY transfers data at a higher data rate relative to the DFI clock and the MC has the option to execute multiple commands in a single DFI clock cycle.
The DFI specification supports a 1:1, 1:2 or 1:4 MC to PHY frequency ratio, defining the relationship of the reference clocks for the MC and the PHY.
Frequency ratio allows the DRAM to run at higher frequencies with a memory controller (and SOC) that run at a lower frequency. Running memory at a higher frequency certainly has the potential for higher performance. But the actual performance of the system will depend on many factors. The utilization when using frequency ratio may be lower depending on how optimally the MC can schedule commands in this mode of operation. But even if the utilization is not as optimized, the 2X (or 4X) memory clock frequency may still be a significant performance increase.
Comparative Study of Frequency Ratios
The following table shows a comparison of “CPU time” consumed by a reference testcase from DFI VIP on VCS :
Frequency Ratio / CPU time1:1 / 2.040 seconds
1:2 / 1.950 seconds
1:4 / 1.840 seconds
The above table shows improvements in CPU time as we move towards 1:4 ratio from 1:1 ratio. This is a big improvement with a single testcase, imagine when huge number of testcases are run, and with an actual DUT design !
The DFI specification defines a frequency change protocol between the MC and the PHY to allow the devices to change the clock frequency of the memory controller and PHY without completely re-setting the system.
Salient Features of DFI Protocol
No restrictions on MC or PHY - The DFI protocol does not encompass all of the features of the MC or the PHY, nor does the protocol put any restrictions on how the MC or the PHY interface to other aspects of the system.
Data Bus Inversion - DBI can be used for reducing the number of transitions on the bus and/or reducing the noise and power consumption on the bus.
DFI read and write training operations can increase accuracy of signal placement at higher speeds in DDR4, DDR3, LPDDR4, LPDDR3 and LPDDR2 systems.
Low Power Mode - If the PHY has knowledge that the DFI will be idle for a period of time, the PHY may be able to enter a MC-initiated low power state.
DFI Protocol Evolution
The latest DFI specs version is Version 4.0, Revision 2. The specs has undergone several major enhancements over the years and following is brief history :
Version / Feature Updates1.0 / Initial Release
2.0 / DDR3 support
2.1 / LPDDR2 support
3.0 / DDR4 support
3.1 / LPDDR3 support
4.0 R2 / LPDDR4 support (Latest)
Stay tuned for more…