CSE271 PennStateUniversity 1/7/2007 Kyusun Choi
Homework 1 Guide
One can check the Xilinx ISE 8 Tutorial at the following link:
Reading the documentation may save your time.
Before starting the homework, you will need to create a folder first.
From the Start menu, click 'My Computer' and create C:\cse271 folder and collect all your homework projects in this folder.
Start the ISE Project Navigator.
Under the File pull down menu, select the New Project…
Before typing the Project Name, you must specify Project Location. Specify C:\cse271 folder that was just created.
Now type the project name. In this case, you will be creating the Homework 1 project and you will be turning in your project as your homework, so you mustname the project with your last name. Make the project name as your last name after "hw1_". For example, my project name will be 'hw1_choi'. Keeping this project/folder name convention is important, for you to get full credit of your work. When I name my project hw1_choi, the ISE program will create a sub-folder C:\cse271\ hw1_choi and collects all the project files in it. If your last name is longer than 8 characters, use only the first 8 characterof your last name.
Select the following properties into the homework 1 project wizard window. These same properties will be used for all the homework.
Family => Spartan3 Top-Level Source Type => HDL
Device => XC3S200 Synthesis Tool => XST (VHDL/Verilog)
Package => FT256 Simulator => ModelsimXE VHDL
Speed => -4
Click Next on the subsequent window.
Again click Next on the subsequent window.
Check the properties and click Next on the subsequent window.
You will see the similar ISE project navigator window shown below. Right click the device xc3s200-4ft256 and select the New Source… option.
Now select the Schematic on the left and type the file name. In this case, you will be creating a file with an AND gate. Also, ALL file names must contain your initials in the beginning. For example, my file name with 2-input AND gate circuit will be 'kcand2' for my first name initial "k" and my last name initial "c" is added to the beginning of the file name. Keeping this file name convention is important, for you to get full credit of your work.
Once you see the ISE project navigator window similar to the one below, click on the kcand2.sch tab on lower right (next to Design Summary tab).
And Maximize the ISE window as shown below.
Scroll the Symbols window list on the left and click the and2 item.
Move the cursor to the right, on the kcand2.sch window and click. Center the 2 input AND gate symbol and click zoom in. The AND gate symbol will follow the cursor, hit Esc key on you key board to end the Insert Symbol mode.
Click Add Wire button and add wires to AND2 gate symbol.
Add wires to all of AND2 gate input and output. Click on Add I/O Maker button and click on the wire ends to put I/O to wires.
Double click on the I/O, and change I/O names to ‘a’, ‘b’, and ‘z’.
Click Save button to save the schematic file just created. Then click Sources tab and Processes tab on the left side of the ISE window.
Double click Synthesize – XST on the left Processes window.
You must see the green check mark, otherwise check the error message and correct your schematic design. WARNING on the Console window can be ignored.
Now right click on the kcand2 in the left Sources window and select New Source… option.
And type the file name, name with TBW – Test Bench WaveForm – to test your design.
You will see the following screen.
Select the following options and click Finish.
You will see the following screen.
Zoom in and click the blue tic marks to create your own input signals. Then click Save button.
Now go to Sources for: box selection on the upper left (above Sources window) and select Behavioral Simulation option.
Then double click Simulate Behavioral Model under the ModelSim Simulator in Processes window.
ModelSim starts and may ends with the following error: “# XE version supports only a single HDL”
Quit ModelSim and go back to ISE window. Go to the Sources for: box and select Synthesis/Implement option. Click kcand2 in the Sources window. Expand Design Utilities in the Processes window. Right click on View HDL Functional Model in Processes window and select Properties...
Change the Functional Model Target Language to VHDL as shown below.
Again expand Design Utilities in the Processes window. Right click on View HDL Instantiation Template in Processes window and select Properties...
Change the Instantiation Template Target Language to VHDL as shown below.
Go to the Sources for: box and select Synthesis/Implement option. Click kcand2 in the Sources window. Double click Synthesize – XST on the left Processes window. Be sure to check the green check mark on the Synthesize.
Now go to Sources for: box selection on the upper left (above Sources window) and select Behavioral Simulation option. Then double click Simulate Behavioral Model under the ModelSim Simulator in Processes window. ModelSim starts and may ends without errors, green lines and blue lines. You may need to play with ModelSim window partition and zooming.
Make an observation and check to see if the output signal ‘z’ is correct. You may print the ModelSim output wave. Or capture the ModelSim window with Alt-Print Screen key and paste it on a MS Word file.
Quit ModelSim. Go to ISE window. Select the option Cleanup Project Files. Now the Homework 1 is almost ready to turn-in. Quit ISE. In your C:\cse271 folder, you will see hw1_yourname sub-folder. ZIP it and email the hw1_yourname.zip file, as an email attachment, to and