Department of

Computer Science and Engineering

Digital System Design (ACOE361)

Experiment #6

CPU Design

Student’s Name:
Semester: / Date:

Assessment:

Assessment Point / Weight / Grade
Methodology
Presentation and discussion of results
Participation

Assessment Points’ Grade

Comments:

Experiment #6:CPU Design

Objectives:

Design, simulate, hardware implement and test a full computer datapath.

Conventions:

The symbol indicates an operation that must be done in hardware e.g. pressing a button or switch, making a connection on the board, a jumper etc.

The symbol indicates an operation that must be done in software e.g. a command that must be entered, a window that must be opened etc.

Introduction:

The processor in any computer architecture system is divided into the datapath and its controller. The datapath consists of three major components:

a) Register file, which is a set of parallel registers (4 registers x 8 bits in this lab)

b) The microoperations performed on data stored in the register file. In a real system, the data are usually stored in the main memory and instructions such as load (lw = load word) and store (sw = store word) are employed to get the data inside the processor and store the major results back to the memory, respectively.

c) Controller. The controller generates the necessary control signals, according to the instruction format of the instruction being executed. It is mainly used to control the smooth operation of the datapath and memory accesses. For educational purposes, in this lab the data are generated by the user and not by accessing the main memory, using the load command. The operation of the controller is transparent to the user. In depth analysis of a controller is provided during the next lab.

In this lab, the data are entered into the system, stored in predetermined memory locations in the register file, fetched, processed by the ALU and stored again back to the register file. The duration of this procedure from entering the data up to the point of storing the result back to the register file takes only 3 clock cycles. 2 clock cycles for loading the data, 1 clock cycle to evaluate the result and save the result back to the memory. If we had to return the result back to the external main memory a fourth clock cycle would be needed.

Figure 1: Datapath Top Level Schematic.

Figure 2. Register file (4 x 4 bits) top level schematic.

Procedure:

  • Step 1. Describe in VHDL the circuit of Figure 2.
  • Step 2.Describe in VHDL the circuit of Figure 1. The control logic should implement the following code

Loop:# The controller controls the loop, you don’t have to reset

Lw R1, X1# load data X1 to register R1 (R1  Data In)

Lw R2, X2#load data X2 to register R2 (R2  Data In)

Add R3, R1, R2#add R1 and R2 & save it to register R3 (R3  R1 + R2)

  • Step 3. Simulate your design using appropriate data inputs.
  • Step 4. Create a constraints file and assign switches to the data inputs, buttons to clk, rst and cin and LEDs to the outputs of the circuit of Figure 1.
  • Step 5. Implement the circuit of Figure 1.
  • Step 5.Download the design on the FPGA board, and use the switches and buttons to observe the outputs on the LEDs.

Inputs / Outputs
Sw1 / Sw2 / Sw3 / Sw4 / Sw5 / 7S1 / 7S2 / 7S3 / 7S4 / Led1
X / 0 / 0 / 1 / 0
X / 1 / 0 / 1 / 0
X / X / X / X / X
X / X / X / X / X
X / 0 / 0 / 0 / 1
X / 1 / 0 / 1 / 0
X / X / X / X / X
X / X / X / X / X
X / 1 / 1 / 1 / 0
X / 0 / 0 / 0 / 1
X / X / X / X / X
X / X / X / X / X

Table 1: Addition

Questions:

  1. What is the range of 4 bits using unsigned numbers?
  1. What is the range of 4 bits using signed numbers?

4. What is the number of CLBs and equivalent gates used for this design?

5. What is the critical path for this design? What is the maximum frequency of operation? Do you think the circuit is slow or fast?

5.b How many clock cycles does it take to complete each instruction?

Clock-cycles Per Instruction (CPI) is a performance metric for computer systems. What is the CPI for our computer system?

6. If you think the circuit is fast, how can we make this circuit run much faster?

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