NTUEE GIEE

Computer-Aided VLSI System Design

Dft Compiler Lab 1: Insert Scan Chain

Objectives:

In this lab, you will learn:

1. How to insert scan chain into a synthesized gate level design

Copy Files from CSDTA Directory

1. copy all the files into your work directory,

cp –R ~cvsd/06F/DftCompiler/Lab1 .

2. check if you have these files

filename / Description
Lab1_alu_synth.v / synthesized gate level Verilog code for the simple ALU
(no scan chain yet)
DftCompilerLab1.script / scripts to run DftCompiler
.synopsys_dc.setup / Synopsys DftCompiler setup file (same format as DesignCompiler). define search paths, library name etc.

3. Check the contents of these files.

Environment Setup

Please add this line into your .cshrc file.

source /usr/cad/synopsys/CIC/tmax.csh

Invoke DftCompiler

DftCompiler is actually embedded in the Design Compiler. To invoke DftCompiler, you can do either one

dc_shell -db_mode -dcsh_mode(command mode)

dv –dcsh_mode & (GUI mode)

I encourage everybody to use command mode because:

a. command mode helps you to keep a record of what you have done.

b. command mode runs more efficiently than GUI mode.

c. command mode helps you to lookup the manual/reference quickly.

In spite of the above advantages, command mode sometimes is not as good as GUI mode in terms of debugging the schematic problem. We will use command mode throughout this Lab. You are welcome to try the GUI mode by yourself.

NOTE: maybe you see some error message like “Error: current design not defined.” just ignore it for now.

Read Input Files

  1. type these linesto read in CIC .18 library and your gate level netlist.

The “target_library” is written in your .synopsys_dc.setup.

read target_library

read Lab1_alu_synth.v -format Verilog

2. To obtain a timing/area report of your scan_inserted design, type

current_design ALU

report_area > Lab1_alu_synth.area_rpt

report_timing > Lab1_alu_synth.timing_rpt

STEP 1 Scan Ready Synthesis

Although you have done the synthesis before, you did not use the –scan option. This compilation(with –scan option) considers the impact of scan insertion onmission mode constraints duringoptimization. This –scan option causes thecommand to replace all sequentialelements during optimization. Type in these lines.

set_scan_configuration–stylemultiplexed_flip_flop

set_scan_configuration -methodology full_scan

compile -scan

Question: Do you see any warning messages? _____ Can you explain what are the sources of the warnings? ______

Do these warning impact our scan chain insertion? ______

NOTE: The things we have done so faractually should have been done in our last synthesis Lab1. We do them separately here for educational purpose.

STEP 2 Set ATE configuration

To create a test clock waveform, type

create_test_clock -period 100 -waveform {40, 60} find(port, "clk")

STEP 3 Pre-scan Check

This command check if your follow the gate-level scan design rule. Type

check_test

Question 1: How many scan cells do you have? _____

Question 2: How many rule violation do you have? _____

STEP 4 Scan specification

This step tells the Dft Compiler how many scan chains you want. You can also specify the names of scan related pins (scan_enable, scan_in, scan_out). We will let Dft Compiler to choose the pin names for us.

set_scan_configuration -chain_count 1

STEP 5 scan preview

This step checks your scan specification for consistency. Please type

preview_scan

Questions: How many scan chains will you have? _____What are their pin names? ______

STEP 6 scan chain synthesis

stitch your scan cells into a chain. And do some more optimizations.

insert_scan

STEP 7 post scan check

To obtain a final summary of your scan chain, type

check_test

STEP 8 Reports

1. To obtain a timing/area report of your scan_inserted design, type

report_area > Lab1_alu_dft.area_rpt

report_timing > Lab1_alu_dft.timing_rpt

Examine the report files of our scan_inserted design. Compare these reports with those of the non-scan design. Answer these questions if you kept a timing and area report of synthesis lab 1.

Questions: How much is the area overhead of scan? ______%

How much is the timing overhead of scan? ____%

2. If you want to know the order of your scan chain, type:

report_test -scan_path > Lab1_alu_dft.scan_path

STEP 9 Write out files

1. To output our scan-inserted netlist, type

write -format verilog -hierarchy -output Lab1_alu_dft.v

2. the spf (Stil Protocol File) file is needed in our next Lab, ATPG.

write_test_protocol -format stil -out Lab1_alu_dft.spf

3. the sdf (standard delay format) file is for timing analysis. Our next tool, Prime time, will need this file.

write_sdf Lab1_alu_dft.sdf

Questions/Comments: Check your Verilog netlist.

1. What type of DFF before dft_compiler? ______What type of DFF after dft_compiler? ______

2. What two pins did dft_compiler add? _

3. Where is scan ouput pin? ___dft_compiler share the scan_output pin with the functional output pin so there is NO dedicated scan output pin. This is done for saving the number of pins. If you want dft_compiler to create a dedicate scan out pin, use this command before you insert the scan chain..

set_scan_configuration -dedicated_scan_port true

We do not do this in this lab.

Congratulations! You have done.

Whatwe have done is in the fileDftCompilerLab1.script.

You can use “include DftCompilerLab1.script” to run it.

END of LAB

Creator:

1st Edition: Chien-Mo Li, 2002

2nd Edition: Yu-Lin Chang, 2004

NTU GIEEComputer Aided System Design 1/4