CMPEN297B Penn State University 3/21/2008 Kyusun Choi
Homework 9 Guide
1. One can carefully check the Xilinx ISE pictures shown in this guide for their Homework 9 completion. Selected schematic design steps has been captured and shown below.
2. Overall Program Counter schematic design is shown below. It consists of 3 sub-circuits: 4bit multiplexer, 4bit flip-flop, and 4bit adder.
3. The 4bit flip-flop design is shown below. Use the D flip-flop ‘FD’ from the ISE library instead of designing your own D flip-flop. (If one designs his/her own D flip-flop circuit, it will work in reality but the circuit may not simulate.)
4. The 4bit 2 to 1 multiplexer design is shown below.
5. The 1 bit 2 to 1 multiplexer design is shown below.
6. The 4bit adder design is shown below.
7. The 1 bit adder circuit design is shown below.
8. The 4bit program counter design is shown below.
9. The 4bit program counter simulation output is shown below.
10. The 4bit program counter simulation zoom-in output is shown below.
11. The 4bit program counter simulation, further zoom-in output is shown below. One may note the fact that the counter is reset in the beginning (first 2 clock cycles) and start counting by 1 (from the 7th clock cycle).
12. The 4bit program counter simulation, further zoom-in output is shown below. One may note the short time of undefined outputs in the beginning of the simulation, which is due to the initialization.
13. The 4bit program counter simulation, further zoom-in output is shown below. One may note the output signal delay from the positive clock signal edge.
14. The 4bit program counter simulation, signal delay measurement is shown below.
15. Extra I/Os are added to the 4bit program counter to observe the intermediate signals.
16. Test Bench Wave form source for the 4bit program counter to observe the intermediate signals is shown. Be sure to choose clocked simulation with CK as clock signal. Choose 20ns high and 20ns low clock, and 5ns setups. Also simulate for 10000ns.
17. Simulation output for the 4bit program counter to observe the intermediate signals is shown.
18. Modification of the 4bit program counter signal into the a(3:0) and b(3:0) buses, for better simulation output readout. A bus signal can be created with simply naming the wire. So create a wire first. Then name the wire a(3:0). Then add the ‘Bus Tap’ to the bus. The Bus Tap symbol can be flipped or rotated for desire orientation. Then connect the Bus Tap wire to other signal wire. In order to connect the wire to a bus, one must rename the wire. In this case, name the wire with a(0), a(1), a(2), or a(3).
19. To be sure, double click the Bus Tap. Following window show the wire connection information on the left side. The net wire a(2) is connected to a(3:0) bus through this Bus Tap.
20. One can also add the I/O Maker to a bus signal.
21. When the schematic is changed, be sure to Save it. Also re-Synthesize and Implement it without error. Warnings are OK.
22. The Test Bench Wave form is now slightly different.
22. Be sure to reset the program counter in the beginning of the simulation and set the b(3:0) input so that the counter output will be other than 0. One can click the bus b(3:0) and type 1 for the input.
23. Simulation output is shown.
24. Zoom-in simulation output. Note that the bus signal output with binary number. One can change the binary number display to integer number display. One can also expand the bus and see the individual signals.
25. Select the signals with left click and then do the right click for Radix display change.
26. Click ‘+’ on the bus signal expands the bus.
27. Test Bench Wave form timing setup example.
28. One can re-design the 4bit multiplexer and the 4bit adder for the bus connection shown below.
29. Example 4bit adder output bus connection.
30. Example 4bit multiplexer input bus connection.
31. Be sure to start early on this homework.