Charnwood Dynamics Ltd

Charnwood Dynamics Ltd.

Hardware Specification

Quad UART Board Rev 2 (DD2396)

Daughter Board Rev 2 (DD2395)

Version: 0.0

Date: 26/02/2003

Author: Simon Hole

Table of Contents

1.0 Introduction / 3
2.0 cPCI Interface / 4
3.0 RS-422 Serial Drive / 5
4.0 Xilinx Timing Generation / 6
5.0 Coda Interface / 9
6.0 Miscellaneous / 12
Appendix / 13

1.0 Introduction

The document is the hardware specification for the Charnwood Dynamics, CompactPCI Quad UART board used in the Coda CX1 Active-Hub. This is essentially a PCI Quad UART with two Coda connectors, mounted with a daughter board with another two Coda connectors on. This gives a total of four 26-way Coda CX1 connectors on the front panel, with four power switches, four power LEDs and two Sync In/Sync Out sockets.

A Xilinx XCR3064 EPLD is used as a Coda Master timing generator, specifically for the ISS project for MIT. The PCB size is CompactPCI Eurocard 160 x 100 mm.

The Quad UART board is part of the Active-Hub unit, which runs an embedded Linux on a PowerPC board. This system is designed to run in real-time, with four Coda CX1s operating in master comms mode, streaming data into the Quad UART board at 5 Mbps per Coda.

Please refer to the component data sheets for accurate and up-to-date information. In addition refer to the schematic diagram to understand how all the components are connected together.

Please refer to the latest parts list for up-to-date component values.

Please refer to the Abel source code for the Xilinx XCR3064 EPLD, for the definition of the EPLD part.

The board has the following key features:

3U CompactPCI PCB format (160 x 100 mm).
5V PCI design (blue) with slave interface.
Four UART channels operating at 5 Mbps.
Four Coda CX1 connectors.
RS-422 serial comms signals.
Xilinx EPLD for Master Sync generation.
+12V fused power to supply four Coda CX1s.
Strobe Output supported.
Sync Input and Output.
+3.3V logic power and +12.0V Coda power.

2.0 cPCI Interface

An Oxford Semiconductor OX16PCI954 Quad UART chip (U1, TQFP160) is used as the interface to the PCI bus. This is an integrated monolithic chip, containing a PCI interface and four high-performance UARTs. The part interfaces directly to the PCI bus via 10R series resistors on all the signal lines except the clock.

A 93C46 SEEPROM (U2, SO-8) can be programmed with addition PCI configuration data for the OX16PCI954. This is done under Windows 98.

The OX16PCI954 chip has the following key features:

OX16PCI954 Integrated PCI and Quad UARTs.
5V PCI Slave Interface.
PCI 2.2 Compliant
PCI Power Management 1.0 compliant.
SEEPROM for additional PCI device configuration.
160 pin TQFP package.
5.0V powered.

A 20.0 MHz oscillator (OSC1, SM) drives the common UART clock to give a maximum data rate of 5 Mbps. Each UART has the following serial line signals:

The OX16PCI954 is configured to operate as four UART and an 8-bit local bus. The Xilinx EPLD is configured off this local bus.

Four IO lines from the OX16PCI954 MIO8, MIO9, MIO10 and MIO11 are used to apply individual resets to each of the Coda CX1s.

Please refer to the OX16PCI954 data sheet for additional information on this powerful device.

3.0 RS-422 Serial Drive

The RX, TX, RTS and CTS signal are TTL level and are converted to RS-422 drive by eight MAX3490E (SO-8) RS-422 transceivers. The MAX3490E contains a Transmitter and a Receiver, which can operate to 12 Mbps and have 15 kV ESD protection.

The RX and CTS receiver RS-422 inputs are each terminated by a 120R 0.5W resistor (2010) to suit the characteristic impedance of the Coda cable.

The RX, TX, RTS and CTS RS-422 signals from each UART all connect to their CODA connectors (J1, J2, J3 and J4).

4.0 Xilinx Timing Generation

A Xilinx XCR3064 EPLD (U3, TQFP44) is interfaced to the 8-bit local bus of the OX16PCI954 Quad UART. This is bridged off the cPCI bus and is I/O mapped onto the Data/Address bus.

The Xilinx EPLD is driven off a 12.000 MHz SM crystal oscillator (50 ppm), to generate the Coda Sync timing sequence. Essentially, a 19-bit counter is used, which allows a minimum EPOCH sample frequencies of 23 Hz. This allows the Coda to sample at 25 and 30 Hz, which are the Television/film frame rates.

The EPLD also controls the Sync source of Interrupt, which can interrupt the cPCI bus.

The EPOCH sample rate generation is given by the following equation:

Timer Value = 12000000 / Epoch Sample Rate

The Epoch Sample Rate can be in the range of 23 to 800 Hz. The 19-bit counter sets the lower limit and the upper limit is set by the Coda CX1 hardware.

4.1 Control Register Definition

The XCR3064 has an 8-bit interface to the backplane, so it can be configured. It has an 8-bit control registers, which is define as follows:

CTRL0

Interrupt Control

0 / Disable Interrupt
1 / Enable External SYNC Interrupt

CTRL1

Interrupt Control

0 / Disable Interrupt
1 / Enable Internal SYNC Generator Interrupt

CTRL2

Counter Control

0 / Disable the 19 bit Counter/Timer
1 / Enable the 19 bit Counter/Timer

Note: this bit is not currently used.

CTRL3

Strobe Unit Control

0 / Disable External STROBE Units
1 / Enable External STROBE Units

CTRL4

Internal SYNC Generator Control

0 / Disable Internal SYNC Generator
1 / Enable Internal SYNC Generator

CTRL5

Coda SYNC Input Control

0 / Disable Coda SYNC Input
1 / Enable Coda SYNC Input

CTRL6

External SYNC Input Control

0 / Disable External SYNC Input
1 / Enable External SYNC Input

CTRL7

External SYNC Polarity Control

0 / External SYNC Input active-low (default)
1 / External SYNC Input active-high

On a Reset the Control Register bits are all set to zero.

4.2 Status Register Definition

This is similar to the Control Register and is defined as follows:

Status Bit

/ Definition
0 / Same as Control Register
1 / Same as Control Register
2 / Same as Control Register
3 / Same as Control Register
4 / Same as Control Register
5 / Same as Control Register
6 / Same as Control Register
7 / Same as Control Register

4.3 Address Decode

4.3 Backplane Address Decode:

A2 /

RD*

WR*

Address Decode

0 / 0 / 0 / 1 / 0 / Control Register 7..0
0 / 0 / 1 / 1 / 0 / -
0 / 1 / 0 / 1 / 0 / -
0 / 1 / 1 / 1 / 0 / -
1 / 0 / 0 / 1 / 0 / Timer Register Byte 0 (LSB)
1 / 0 / 1 / 1 / 0 / Timer Register Byte 1
1 / 1 / 0 / 1 / 0 / Timer Register Byte 2 (MSB)
1 / 1 / 1 / 1 / 0 / -
0 / 0 / 0 / 0 / 1 / Status Register 7..0
0 / 0 / 1 / 0 / 1 / Interrupt Status Register 2..1
0 / 1 / 0 / 0 / 1 / -
0 / 1 / 1 / 0 / 1 / -
1 / 0 / 0 / 0 / 1 / -
1 / 0 / 1 / 0 / 1 / -
1 / 1 / 0 / 0 / 1 / -
1 / 1 / 1 / 0 / 1 / -

4.4 JTAG

The Xilinx XCR3064 EPLD uses a JTAG header (HD8) for programming.

The JTAG header is a 10-way (2x5) double row header defined as follows:

/ Function
1 / 0V
2 / TCK
3 / 0V
4 / TMS
5 / 0V
6 / TDI
7 / 0V
8 / TDO
9 / No Pin (key)
10 / No Connect

5.0 Coda Interface

5.1 Strobe Circuit

The purpose of the strobe circuit is to combine the four StrobeIn* inputs from the Codas and to output the combined signal to a header to drive and external Strobe Unit. The four RS-422 StrobeIn* inputs are each terminated by a 120R resistor, which has bias resistors to ensure the StrobeIn* signal is always de-asserted.

These are converted to TTL by four MAX3490E (U15, U17, U19 and U21) and are combined by a 74LV08 AND gate (U24, SO-14). If any of the StrobeIn* signals are asserted then the combine StrobeIn* will also assert. The StrobeIn* signal is passed through the EPLD to enable or disable it and is output as the StrobeOut* signal.

The StrobeOut* signal is then converted back to RS-422 by a MAX3490E (U21) and put out on HD5. An external Strobe Unit can then be driven off this connector.

HD5 and HD6 Strobe Headers

/ Function
1 / Strobe+
2 / Strobe-
3 / +12V
4 / 0V

5.2 Sync Circuit

The SyncIn* input circuit operates in a similar way to the Strobe input circuit by combining the four SyncIn* inputs from the four Codas. In addition is allows a Master Sync generated by the Xilinx EPLD to be output to all Codas.

The four RS-422 Sync* inputs are each terminated by a 120R resistor, which has bias resistors to ensure the SyncIn* signal is always de-asserted.

These are converted to TTL by four MAX3490E (U14, U16, U18 and U20) and are combined by a 74LV08 AND gate (U23, SO-14). If any of the SyncIn* signals are asserted then the combine SyncIn* will also assert. The SyncIn* signal is passed through the EPLD to multiplex it with the Internal/External Sync and is output as the SyncOut* signal.

The SyncOut* signal is then converted back to four RS-422 signals by four MAX3490Es (U14, U16, U18 and U20) and output to the four Coda connectors. An addition MAX3490E (U19) drives the SyncOut* signal to the external Sync Input/Output header.

The external Sync input is a RS-422 active-low Sync input to synchronise Codas from an external source of timing. This is passed to two monostables, to give a short pulse of 500ns, which is used as the cleaned up Sync pulse and a long pulse of 50ms, which is used to drive an LED and to indicate the presence of an external Sync pulses. The long pulse can be used for to control a Sync Multiplexor, to allow a switch to internal Sync source should the external Sync fail.

HD7 External Sync Input/Output

/ Function
1 / SyncOut+
2 / SyncOut-
3 / ExtSyncIn+
4 / ExtSyncIn-
5 / 0V

This header must be wired to its Sync In and Sync Out LEMO connector on the Front Panel.

5.3 Coda Power

An onboard header HD9 connects the +12V power to the board and onto the four Codas. Each Coda can take a maximum of 1.2A so a total of 4.8A maximum could be required. The Compact PCI connector has a rating of 1.0A for the 12V pin, so this cannot be used. A lead from the PSU is required to apply power to HD9.

HD9 External +12V Power Header

/ Function
1 / +12V
2 / +12V
3 / +12V
4 / 0V
5 / 0V
6 / 0V

The +12V power is applied to four 4-way SIL headers HD1, HD2, HD3 and HD4. Pins 1 and 2 go to the Coda power switch. Pins 3 and 4 go to the LED (+12V LED). The LED is on a cable loopback, so if a cable is not connected then the LED will not light when the power is switched on.

HD1, HD2, HD3 and HD4 Coda Power Header

/ Function
1 / Power Switch (+12V)
2 / Power Switch
3 / LED+
4 / LED-

The +12V to each Coda is passed through a 1.6A PolySwitch fuses F1, F2, F3 and F4 (SM, 1812).

This header must be wired to its switch and LED on the Front Panel.

5.4 Coda USB

Each Coda connector has a 4 way SIL header, which corresponds to a similar header on the SHARC processor board. This was originally designated USB for the ISS project, but are now used as two Spare signal pairs.

HD1A, HD2A, HD3A and HD4A USB headers

/ Function
1 / USB+ (Spare1+)
2 / USB- (Spare1-)
3 / USB Power+ (Spare2+)
4 / USB Power- (Spare2-)

6.0 Miscellaneous

6.1 Environmental

The board will be designed using commercial grade components (0 to +70 C) and will operate within the Active-Hub unit in an ambient temperature of 0 to +55 C.

The Active-Hub unit must protect the board from mechanical shock, vibration, thermal stresses and humidity.

6.2 EMC

The board will be designed for EMC compliance. Input/output signals will be filtered and power supplies will have high-frequency decoupling. Ground plane management will be implemented.

6.3 Components

All surface components will be used wherever possible (except connectors). Discrete resistors and non-polarised capacitors will be 0805 size due to the high board density. Larger sized resistors will be used where greater power dissipation is required.

Components will be mounted on the component (upper) side of the PCB.

All components will be commercial grade (0 to +70 C) and semiconductors will be in plastic packages. The use of IC sockets will be avoided.

6.4 PCB

The PCB will have 4 layers, with inner Ground and Power planes. Tracking will be 8 thou tracking and 8 thou gap.

The Ground plane will be solid with no splits in it. However, there will be a split in the Power plane, so the UART components and tracking will be over the +5V power plane. The remaining digital components and tracking will be over the +3.3V digital power plane.

The silkscreen will be labelled ‘CHARNWOOD DYNAMICS LTD’.

6.5 Connectors

The Coda CX1 connectors are four 26-way High-Density D connectors (J1-J4), which connect to four Coda CX1 units. Two Lemo sockets are used for the RS-422 External SyncIn and SyncOut signals. See the Appendix for the connector pin outs.

APPENDIX

Connector Pin Outs

J1, J2, J3 and J4 – Coda CX1 Connectors

26-way High-Density D Socket

Pin No. / Function
1 / VIN+ (+12V nominally)
2 / TX-
3 / RX+
4 / CTS-
5 / VIN- (0V)
6 / SYNC OUT-
7 / SYNC IN+
8 / USB2/SPARE2
9 / VIN- (0V)
10 / Chassis/Earth
11 / VIN- (0V)
12 / TX+
13 / RTS-
14 / CTS+
15 / STROBE OUT-
16 / SYNC OUT+
17 / USB4/SPARE4
18 / USB1/SPARE1
19 / VIN- (0V)
20 / VIN+ (+12V nominally)
21 / RX-
22 / RTS+
23 / RESET IN*
24 / STROBE OUT+
25 / SYNC IN-
26 / USB3/SPARE3

HD1, HD2, HD3 and HD4 Coda Power Header

4-way SIL Header

/ Function
1 / Power Switch (+12V)
2 / Power Switch
3 / LED+
4 / LED-

HD1A, HD2A, HD3A and HD4A USB headers

4-way SIL Header

/ Function
1 / USB+ (Spare1+)
2 / USB- (Spare1-)
3 / USB Power+ (Spare2+)
4 / USB Power- (Spare2-)

HD5 and HD6 Strobe Headers

4-way SIL Header

/ Function
1 / Strobe+
2 / Strobe-
3 / +12V
4 / 0V

HD7 External Sync Input/Output

5-way SIL Header

/ Function
1 / SyncOut+
2 / SyncOut-
3 / ExtSyncIn+
4 / ExtSyncIn-
5 / 0V

HD8 – JTAG Connector

10-way (2x5) Header

/ Function
1 / 0V
2 / TCK
3 / 0V
4 / TMS
5 / 0V
6 / TDI
7 / 0V
8 / TDO
9 / No Pin (key)
10 / No Connect

HD9 External +12V Power Header

6-way SIL Header with Friction Lock

/ Function
1 / +12V
2 / +12V
3 / +12V
4 / 0V
5 / 0V
6 / 0V

Xilinx XCR3064 ABEL Source Code

MODULE Decoder

TITLE 'CoolRunner_cPCI_QuadUart_Board'

// CoolRunner CPLD on the cPCI Quad UART Board.

// This is the Master Timing Generator for a slave CX1 Coda.

// XCR3064XLXCR3064XL using WebPACK ISE.

//*******************************************************************

// Local Bus Address Decode

// A0, A1, A2, A3 Address Bus & D0-D7 Data Bus

// A4, A5, A6, A7 Not Connected

// Local Bus ADDRESS:

// 0x0000 = Control/Status Register.

// 0x0001 = Interrupt Status Register.

// 0x0002 = TBD.

// 0x0003 = TBD.

// 0x0004 = Timer Byte 0 (LSB)

// 0x0005 = Timer Byte 1

// 0x0006 = Timer Byte 2 (MSB)

// 0x0007 = TBD

//*******************************************************************

// 29/06/2001Created.

// 10/09/2001Modified to the PCB pinout, to include SYNC generation

//capabilty, with Sync and Strobe inputs. Support for

//180 Hz mode required.

//Require 60, 100, 120, 180, 200, 400 & 800 Hz EPOCH rates

// 26/09/2001Address Map added.

// 27/09/2001Programmable 24-bit Timer added for sample rate generation.

// 05/12/2001Ported to the cPCI design on the OX16PCI954 local bus.

//This has an 8 bit data bus.

// 02/01/2002Use a 19 bit counter to reduce the number of nodes.

//This will give a 23 Hz Min. EPOCH Rate.

// 18/02/2002cPCI Quad UART board is now in PCB CAD. Pinout reflects

//the schematic.

// 16/02/2002MIO0 to MIO3 made Active-High. OXPROM adjusted for active-

//high INTs.

// 29/04/2002 bug-fix: DATA8.OE was active-low, made active-high.

// 30/04/2002MIO0 will support Ext. Sync Input and

//MIO1 will support Int. Sync Generator PCI Interrupts.

//These must be latched. CTRL0 & CTRL1 are Int. enable bits.

//Do not write 0 to the Timer registers as this will cause

//an infinitely wide SYNC pulse.

//May need to condition the External Sync Input, due to the

//wired-OR nature of PCI interrupts. Using EXT_SYNC_SHORT#,

//to prevent this.

//***********************************************************************

// RESET = all ZERO:

// CTRL0 = 0 : Disable Interrupt.

// = 1 : Enable External Sync input Interrupt.

// CTRL1 = 0 : Disable Interrupt.

// = 1 : Enable Internal Sync Generator Interrupt.

// CTRL2 = 0 : Disable the 19 bit Counter/Timer// Not currently used

// = 1 : Enable the 19 bit Counter/Timer// Not currently used

// CTRL3 = 0 : Disable External STROBE Units

// = 1 : Enable External STROBE Units

// CTRL4 = 0 : Disable Internal SYNC Generator

// = 1 : Enable Internal SYNC Generator

// CTRL5 = 0 : Disable Ext CODA SYNC Input

// = 1 : Enable Ext CODA SYNC Input

// CTRL6 = 0 : Disable Ext SYNC Input

// = 1 : Enable Ext SYNC Input

// CTRL7 = 0 : Ext SYNC Input : active-low (default)

// = 1 : Ext SYNC Input : active-high

//***********************************************************************

// PIN Definitions

// Local Bus Signals

nRSTPIN 38;// : Active-Low

nCS0PIN 39;// : Active-Low

nRDPIN 37;// : Active-Low

nWRPIN 35;// : Active-Low

A0PIN 21;// :

A1PIN 22;// :

A2PIN 23;// :

A3PIN 27;// :

D0PIN 20;// : D0

D1PIN 19;// : D1

D2PIN 18;// : D2

D3PIN 15;// : D3

D4PIN 14;// : D4

D5PIN 13;// : D5

D6PIN 12;// : D6

D7PIN 11;// : D7

// CODA SYNC Signals - ANDed together externally.

CLK12PIN 40;// 12 MHz Clock input

nCODA_SYNC_INPIN 44;// CODA SYNC IN: Active-Low

EXT_SYNC_INPIN 3;// EXT_SYNC_IN: Active Low or High

nEXT_SYNC_OUTPIN 5 istype 'com';// EXT_SYNC_OUT: Active-Low (to mono stable)

nEXT_SYNC_SHORTPIN 6;// EXT_SYNC: Active-Low (from mono stable)

EXT_SYNC_LONGPIN 8;// EXT_SYNC: Active-High (from mono stable)

// High when External Sync Present.

// Bit 0 in Control/Status Register.

nSYNCPIN 10 istype 'com';// SYNC: Active-Low

// CODA STROBE Signals.

nSTROBE_INPIN 43;// STROBE IN: Active-Low

nSTROBE_OUTPIN 42 istype 'com';// STROBE OUT: Active-Low to Ext Strobe Units

// Interrupt Signals to OX16PCI954

MIO0PIN 34 istype 'com';// Active-High

MIO1PIN 33 istype 'com';// Active-High

MIO2PIN 31 istype 'com';// Active-High

MIO3PIN 30 istype 'com';// Active-High

// NODE Definitions

CTRL7..CTRL0NODE istype 'reg, buffer';// 8-bit Control Register

Q18..Q0NODE istype 'reg, buffer';// 19-bit Counter

INT_SYNC1NODE istype 'reg, buffer';// Internal SYNC FF1

INT_SYNC2NODE istype 'reg, buffer';// Internal SYNC FF2

INT_SYNC3NODE istype 'reg, buffer';// Internal SYNC FF3

nSYNC_GENNODE istype 'buffer';// Internal SYNC Generator Output

TIMA7..TIMA0NODE istype 'reg, buffer';//

TIMB7..TIMB0NODE istype 'reg, buffer';//

TIMC2..TIMC0NODE istype 'reg, buffer';//

LOADNODE istype 'buffer';// Pre-Load the Timer/Counter

LOAD1NODE istype 'buffer';// Counter Load Signal

EXT_SYNC_INTNODE istype 'reg, buffer';// PCI Interrupt Latch bit

INT_SYNC_INTNODE istype 'reg, buffer';// PCI Interrupt Latch bit

EXT_SYNC1NODE istype 'reg, buffer';// Ext Sync Synchronisation FF

EXT_SYNC2NODE istype 'reg, buffer';// Ext Sync Synchronisation FF

// SET Declaration

CONTROL= [CTRL7..CTRL0];// 8-bit Control Reg.

TIMERA= [TIMA7..TIMA0];// 8-bit Timer Reg.

TIMERB= [TIMB7..TIMB0];// 8-bit Timer Reg.

TIMERC= [TIMC2..TIMC0];// 3-bit Timer Reg.

TIMER= [TIMERC, TIMERB, TIMERA];// 19-bit Timer Reg.

DATAB8= [D7..D0];// 8-bit Data Bus D0->D7

DATAB3= [D2..D0];// 4-bit Data Bus D0->D3

COUNTER= [Q18..Q0];// 19-bit Counter

//***********************************************************************

EQUATIONS

// SYNC Generation (active-low)

nSYNC = !((!nSYNC_GEN & CTRL4) #// Internal SYNC Generator

(!nCODA_SYNC_IN & CTRL5) #// CODA SYNC input

(!nEXT_SYNC_SHORT & CTRL6));// External SYNC input (500 ns)

nEXT_SYNC_OUT = !((!EXT_SYNC_IN & !CTRL7) #// EXT_SYNC: Active-Low (to monostable)

( EXT_SYNC_IN & CTRL7));// EXT_SYNC: Active-High (to monostable)

// Enable the External STROBE Units

nSTROBE_OUT = !(!nSTROBE_IN & CTRL3);

// cPCI IRQ Generation// MIO0 -> MIO3 are driven active-high

// 30.04.2002

MIO0 = EXT_SYNC_INT & CTRL0;// EXT SYNC input PCI Interrupt.

MIO1 = INT_SYNC_INT & CTRL1;// INT SYNC Gen PCI Interrupt.

MIO2 = 0;//

MIO3 = 0;//

// Reading the following two Interrupt Status Registers will clear them!

// They are SET whether or not the actual interrupts are enabled.

EXT_SYNC_INT.D = 0;

EXT_SYNC_INT.CLK = !(nRST & !nCS0 & !nRD & !A3 & !A2 & !A1 & A0);// Address 1, Bit 0

EXT_SYNC_INT.PR = !nEXT_SYNC_SHORT;// Active-low

EXT_SYNC_INT.AR = !nRST;

INT_SYNC_INT.D = 0;

INT_SYNC_INT.CLK = !(nRST & !nCS0 & !nRD & !A3 & !A2 & !A1 & A0);// Address 1, Bit 1

INT_SYNC_INT.PR = INT_SYNC1;// Active-high

INT_SYNC_INT.AR = !nRST;

// Control Reg Decode - Address = 0x0000

CONTROL.D= [D7..D0];

CONTROL.CLK= !(nRST & !nCS0 & !nWR & !A3 & !A2 & !A1 & !A0);// Address 0

CONTROL.AR= !nRST;

// 30.04.2002

//DATAB8= [CTRL7..CTRL2, 0, EXT_SYNC_LONG];

DATAB8= [CTRL7..CTRL0] & !A0 #// Address 0

[CTRL7..CTRL2, INT_SYNC_INT, EXT_SYNC_INT] & A0;// Address 1

// 29.04.2002

//DATAB8.OE= !(nRST & !nCS0 & !nRD & !A3 & !A2 & !A1 & !A0);

DATAB8.OE= (nRST & !nCS0 & !nRD & !A3 & !A2 & !A1);// Address 0 & 1

// Timer Register Decode Address = 0x0004, 0x0005, & 0x0006

TIMERA.D= DATAB8;

TIMERA.CLK= !(nRST & !nCS0 & !nWR & !A3 & A2 & !A1 & !A0); // Address 4