Chapter 8 – Central Processing Unit

Section 8.1 – Introduction

  • The CPU is made up of three major parts, as shown in Fig. 8-1.

Section 8.2 – General Register Organization

  • For example, to perform the operation R1  R2 + R3, the control must provide binary selection variables to the following selector inputs:
  1. SELA to place the content of R2 into bus A.
  2. SELB to place the content of R3 into bus B.
  3. OPR to provide arithmetic addition A + B
  4. SELD to transfer the content of the output bus into R1.
  • These four selection variables are generated in the control unit and must be available at the beginning of the clock cycle. On the next clock transition, the output on the bus is transferred into R1.

The control words for few of the microoperations are shown in Table 8.3.

Section 8.4 – Instruction Formats

  • It is the function of the control unit within the CPU to interpret each instruction code
  • The bits of the instruction are divided into groups called fields
  • The most common fields are:
  • Operation code
  • Address field – memory address or a processor register
  • Mode field – specifies the way the operand or effective address is determined
  • A register address is a binary number of k bits that defines one of 2k registers in the CPU
  • The instructions may have several different lengths containing varying number of addresses
  • The number of address fields in the instruction format of a computer depends on the internal organization of its registers
  • Most computers fall into one of the three following organizations:
  • Single accumulator organization
  • General register organization
  • Stack organization
  • Single accumulator org. uses one address field. All operations are performed with an implied accumulator register

ADDX results in the operation AC  AC + M[X]

  • The general register org. uses three address fields

ADDR1, R2, R3 results in the operation R1  R2 + R3

  • Can use two rather than three fields if the destination is assumed to be one of the source registers

ADD R1, R2 results in the operation R1  R1 + R2

ADD R1, X results in the operation R1R1 + M[X]

  • Stack org. would require one address field for PUSH/POP operations and none for operation-type instructions

PUSHX

ADD

  • Some computers combine features from more than one organizational structure

Example: X = (A+B)  (C + D)

Three-address instructions:

ADDR1, A, BR1  M[A] + M[B]

ADDR2, C, DR2  M[C] + M[D]

MULX, R1, R2M[X]  R1  R2

Two-address instructions:

MOVR1, AR1  M[A]

ADDR1, BR1  R1 + M[B]

MOVR2, CR2  M[C]

ADDR2, DR2  R2 + M[D]

MULR1, R2R1  R1  R2

MOVX, R1M[X]  R1

One-address instructions:

LOAD AAC  M[A]

ADD BAC  AC + M[B]

STORE TM[T]  AC

LOAD CAC  M[C]

ADD DAC  AC + M[D]

MUL TAC  AC  M[T]

STORE XM[X]  AC

Zero-address instructions: (TOS stands for top of stack)

PUSH ATOS  A

PUSH BTOS B

ADDTOS  (A +B)

PUSH CTOS  C

PUSH DTOS  D

ADDTOS  (C + D)

MULTOS  (C + D)  (A + B)

POP XM[X]  TOS

RISC instructions:

  • Restricted to the use of LOAD and STORE instructions when communicating between memory and CPU. All other instructions are executed within the registers of the CPU without referencing to memory.

LOAD R1, AR1  M[A]

LOAD R2, BR2  M[B]

LOAD R3, CR3  M[C]

LOAD R4, DR4  M[D]

ADD R1, R1, R2R1  R1 + R2

ADD R3, R3, R4R3  R3 + R4

MUL R1, R1, R3R1  R1  R3

STORE X, R1M[X]  R1

Section 8.5 – Addressing Modes

  • The addressing mode specifies a rule for interpreting or modifying the address field of the instruction before the operand is actually referenced
  • The decoding step in the instruction cycle determines the operation to be performed, the addressing mode of the instruction, and the location of the operands
  • Two addressing modes require no address fields – the implied mode and immediate mode
  • Implied mode: the operands are specified implicitly in the definition of the instruction – complement accumulator or zero-address instructions in a stack-organized computer
  • Immediate mode: the operand is specified in the instruction
  • Register mode: the operands are in registers
  • Register indirect mode: the instruction specifies a register that contains the address of the operand
  • Autoincrement or Autodecrement mode: similar to the register indirect mode except that the register is incremented or decremented after (or before) its value is used to access memory
  • Direct address mode: the operand is located at the specified address given
  • Indirect address mode: the address specifies the effective address of the operand
  • Relative address mode: the effective address is the summation of the address field and the content of the PC
  • Indexed addressing mode: the effective address is the summation of an index register and the address field
  • Base register address mode: the effective address is the summation of a base register and the address field

Section 8.6 – Data Transfer and Manipulation

  • There is a basic set of operations that most computers include in their instruction set
  • The opcode and/or symbolic code may differ for the same instruction among different computers
  • There are three main categories of computer instructions:
  • Data transfer instructions
  • Data manipulation instructions
  • Program controlinstructions
  • Data transfer instructions: transfer data from one location to another without changing the binary information content

Load LDInput IN

Store STOutput OUT

Move MOVPush PUSH

Exchange XCHPop POP

  • Some assembly language conventions modify the mnemonic symbol to

differentiate between addressing modes

  • LDI – load immediate
  • Someuse a special character to designate the mode
  • Data manipulationinstructions: perform arithmetic, logic, and/or shiftoperation
  • Arithmetic instructions:

IncrementINCDivideDIV

DecrementDECAdd with carryADDC

AddADDSubtract with borrowSUBB

SubtractSUBNegate (2’s comp)NEG

MultiplyMUL

  • Somecomputers have different instructions depending upon the data type

ADDIAdd two binary integer numbers

ADDFAdd two floating point numbers

ADDDAdd two decimal numbers in BCD

  • Logical and bitmanipulation instructions:

ClearCLRClear carryCLRC

ComplementCOMSet carrySETC

ANDANDComplement carryCOMC

OROREnable interruptEI

Exclusive ORXORDisable interruptDI

  • Clearselected bits – AND instruction
  • Setselected bits – OR instruction
  • Complement selected bits– XOR instruction
  • Shiftinstructions:

Logical shift rightSHRRotate rightROR

Logical shift leftSHLRotate leftROL

Arithmetic shift rightSHRAROR thru carryRORC

Arithmetic shift leftSHLAROL thru carryROLC

  • An instruction code format of a shift instruction with five fields is as follows:

OP REG TYPE RL COUNT

Section 8.7 – Program Control

  • Program controlinstructions: provide decision-making capabilities and change the programpath
  • Typically, the programcounter is incremented during the fetch phase to the location of the nextinstruction
  • Aprogram control type of instruction may change the address value in the programcounter and cause the flow of control to be altered
  • Thisprovides control over the flow of program execution and a capability forbranching to different program segments

BranchBRReturnRET

JumpJMPCompareCMP

SkipSKPTestTST

CallCALL

  • TSTand CMP cause branches based upon four status bits: C, S, Z, and V

Status Bit Conditions:

  • Bit C (carry) is set to 1 if the end carry C8 is 1.
  • Bit S (sign) is set to 1 if F7 is 1.
  • Bit Z (zero) is set to 1 if output of the ALU has all 0’s.
  • Bit V (overflow) is set to 1 if the XOR of the last two carries is equal to 1.

Conditional Branch Instructions:

Subroutine Call and Return:

  • Acall subroutine instruction consists of an operation code together with anaddress that specifies the beginning of the subroutine
  • Execution of CALL:
  • Temporarily store returnaddress
  • Transfer control to thebeginning of the subroutine – update PC

SPSP - 1

M[SP]PC

PCeffective address

  • Execution of RET:
  • Transfer return addressfrom the temporary location to the PC

PCM[SP]

SPSP+ 1

  • Program interruptrefers to the transfer of program control to a service routine as a result ofinterrupt request
  • Control returns to theoriginal program after the service program is executed
  • Aninterrupt procedure is similar to a subroutine call except:
  • Theinterrupt is usually initiated by an internal or external signal rather than aninstruction
  • Theaddress of the interrupt service routine is determined by the hardware ratherthan the address field of an instruction
  • Allinformation necessary to define the state of the CPU is stored rather than justthe return address
  • Theinterrupted program should resume exactly as if nothing had happened
  • Thestate of the CPU at the end of the execute cycle is determined from:
  • Thecontent of the PC
  • Thecontent of all processor registers
  • Thecontent of certain status conditions
  • Theprogram status word(PSW) is a register that holds the status and controlflag conditions
  • Notall computers store the register contents when responding to an interrupt. In this case the service program must include instructions to store status and register content before these resources are used.
  • The hardware procedure for processing an interrupt is very similar to the execution of a subroutine call instruction.
  • TheCPU does not respond to an interrupt until the end of an instruction execution.
  • Thecontrol checks for any interrupt signals before entering the next fetch phase
  • During the interrupt cycle, the contents of PC and PSW are pushed onto the stack, and the branch address for the particular interrupt is then transferred to PC and a new PSW is loaded into the status register.
  • The last instruction in the service program is a return from interrupt instruction.
  • Threetypes of interrupts:
  • External interrupts
  • Internal interrupts
  • Software interrupts
  • Externalinterruptscome from I/O devices, timing devices, or any other externalsource (ex: I/O device requesting data transfer, power failure etc;)
  • Internalinterruptsarise from illegal or erroneous use of an instruction or data,also called traps (ex: register overflow, divide by zero etc;)
  • Internal interrupts aresynchronous while external ones are asynchronous
  • Bothare initiated from signals that occur in the hardware of the CPU
  • Asoftware interrupt is initiated by executing an instruction

Section 8.8 – Reduced Instruction Set Computer (RISC)

  • Animportant aspect of computer architecture is the design of the instruction setfor the processor
  • Theinstruction set determines the way that machine language programs areconstructed
  • Manycomputers have instructions sets of about 100 - 250 instructions
  • Thesecomputers employ a variety of data types and a large number of addressing modes– complex instruction set computer (CISC)
  • ARISC uses fewer instructions with simple constructs so they can be executed muchfaster within the CPU without often using the memory
  • Theessential goal of a CISC architecture is to attemptto provide a single machineinstruction for each statement that is written in a high-level language
  • Themajor characteristics of CISC architecture are:
  • Large number ofinstructions
  • Someinstructions that perform specialized tasks and are used infrequently
  • Large variety ofaddressing modes
  • Variable lengthinstruction formats
  • Instructions thatmanipulate operands in memory
  • Thegoal of RISC architecture is to reduce execution time by simplifying theinstructions set
  • Themajor characteristics of RISC architecture are:
  • Relatively fewinstructions
  • Relatively fewaddressing modes
  • Memory access limited toload and store instructions
  • Alloperations done within the registers of the CPU
  • Fixed-length, easilydecoded instruction format
  • Single-cycle instructionexecution
  • Hardwired rather thanmicroprogrammed control
  • Relatively large numberof registers in the processor unit
  • Useof overlapped register windows to speed-up procedure call and return
  • Efficient instructionpipeline
  • Ability to execute oneinstruction per clock cycle
  • Compiler support forefficient translation of high-level language programs into machine languageprograms
  • Overlapped register windowsare used to pass parameters and avoids the need for saving andrestoring register values during procedure calls
  • Eachprocedure call activates a new register window by incrementing a pointer, whilethe return statement decrements the pointer and causes the activation of theprevious window
  • Windows for adjacentprocedures have overlapping registers that are shared to provide the passing ofparameters and results
  • Example: system with 74registers and four procedures
  • Eachprocedure has a total of 32 registers while active
  • 10global registers
  • 10local registers
  • 6low overlapping registers
  • 6high overlapping registers
  • Relationships of registerwindows
  • # ofglobal registers = G (10)
  • # oflocal registers in each window = L (10)
  • # ofcommon registers to two windows = C (6)
  • # ofwindows = W (4)
  • window size = L + 2C + G
  • total # of registers =(L + C)W + G