Before-Class Lab
Before-Class Lab
Introduction
This lab can be completed while waiting for class to start. You do not have to have any experience with the Xilinx software to perform the lab. (If you are already familiar with Xilinx, you should still do this lab to generate files that will be examined in detail during the class. This will allow you time to do other variations on the labs in the class.)
A simple schematic of an 8-bit counter has been entered for you, and you will translate it and download it to the demo board.
Objective
Introduce you to a small counter design that will be used during the class.
Introduce you to the Xilinx Foundation Project Manager (Design Entry Tools).
Introduce you to the Xilinx Foundation M1-based Implementation Tools.
Show the basics of using the Design Manager, and Flow Engine programs.
Use the automatic translation process on a pre-entered schematic.
Gain experience with the XS40 or the Xilinx demo board.
Procedure
This is an eight-bit binary counter using the standard Xilinx macro library. It is targeted for the XC4000 family, but the same macro also supports other Xilinx families.
This a loadable, bidirectional counter. The load control and data inputs connect to toggle switches on the demo board. The Clock Enable also connects to a toggle switch, while the clock is generated inside the FPGA. The outputs will be visible on LEDs on the demo board.
Procedure
1)From the Windows Program Manager, clickStart Programs Xilinx Foundation Series Foundation Project Manager.
All of the lab files which constitute the actual projects are located underneath the C:\F14_labs directory. The project manager defaults initially to the C:\Fndtn\active\projects directory
2)To open the COUNT Project in the FLOW directory:
A) File Open Project...
B) Under Directories, double-click the [..] three times to traverse to the root level.
Go to the C:\F14_labs\flow directory, so that Path says “c:\f14_labs\flow”.
C) Select the Project COUNT
D) SelectOpen
3)Open the schematic by clicking the Schematic Editor icon. Now browse around this design. Take a moment to use the navigation tools and the
Hierarchy button to navigate into and out of schematic blocks.
4)Save the schematic to update the schematic netlist. Select File Save As... click on COUNT <OK> Yes.
5)Return to the Foundation Project Manager.
You may use <Alt> + <Tab> to change windows, or File Exit to close the Schematic Editor.
6)Select the “Implement M1” icon, and then Yes (responding to request to update netlist). Before opening the Xilinx M1-based implementation tools, the Foundation Project Manager will convert the schematic netlist to an EDIF netlist.
7)You are now in the Xilinx Design Manager. We will “Implement” the newly translated netlist files just created. The automatic translate occurred when we clicked on the “Implement M1” button and entered the Design Manager. This step merges several Xilinx Netlist Files or EDIF format files together into one.
8)Implement the design, with the option to generate a timing report:
A)Design Implement... Options,
B)Check the “Produce Post Layout Timing Report” box .
C)Hit<OK> Run
This will open the Flow Engine (and generate a post layout timing report), showing the progress of the implementation process. The Flow Engine runs several programs to complete the translation from the Xilinx design netlist to the Xilinx configuration file (bitstream). The default options are being used.
As the Flow Engine is running, selectUtilities Report Browser. When available, double-click the Place & Route Report. Find the number of CLBs (logic blocks) used. Record this number here.______
When available, double-click the Post Layout Timing Report, and find the system speed performance. Record these here. ______
1)ClickOK> when the Design Manager reports the implementation process completed successfully.
Downloading a Design to the Xilinx DemoBoard
2)Turn on the power to the demo board (see “Downloading to Xilinx Demo Boards” for details.)
3)Download the design bitstream:
4)Create a DOS session.
5)SelectStart Run…, type”cmd”, click on <OK>.
6)Type”cd \f14_labs\flow\count”.
7)Type“xsload count.bit”.
8)Verify the design functionality (see “Controlling the Counter”). Exit the DOS session when done by typing “Exit”.
QUESTIONS (Optional)
1) About how fast does the counter appear to be running? ...... Hz
(You can count the number of seconds the MSB is on or off, and divide this into 128).
Note that this is not the maximum speed the chip can meet, but only a reflection of the clock speed being applied to the design. In this design, the clock is generated by an internal oscillator referenced through the OSC4 primitive.
What is the OSC4 output frequency being used in the schematic? ...... Hz
Is this comparable to the frequency you observed above?
Yes No
2) Which has higher priority, Clock Enable or Load? Clock Enable Load
3) How is this achieved? Examine the Libraries Guide for the CB8CLED macro and the FTCLE macro that defines the flip-flops. Use the on-line books for the Libraries Guide:
A)Start Programs Xilinx Foundation Series Online Books
B)Click on Xilinx Books under the Collection window.
C)In the Find window, type“CB8CLED” <enter>. Notice that there are 7 occurances of this word in the Libraries Guide.
D)Double-click the Libraries Guide under the Title window.
E)Use the search arrows to find the CB8CLED macro. Click on its hotlinks to get to the full description.
......
......
4) How much of the device was used by this design (look at the Placement Report)?
...... % of the CLBs
5) What is the maximum net delay in the design? (See the Post Layout Timing Report.) What is the maximum clock frequency that can used for this design? What is the difference?
......
......
......
Before-Class Lab Answers
1) About how fast does the counter appear to be running? 10-15 Hz
What is the OSC4 output frequency being used in the schematic? 15 Hz
Is this comparable to the frequency you observed above?
YesNo
The actual frequency can range between 50% and 150% of the value (7.5 to 22.5 Hz), because the oscillator being used is not designed to be accurate.
2) Which has higher priority? Clock Enable Load
3) How is this achieved?
The FTCLE macro includes an OR gate on the flip-flop’s clock enable line that allows either CE or LD to enable the clock.
4) How much of the device was used by this design?
...4% of the CLBs, from the Place & Route Report
Device utilization summary:
Number of External IOBs 17 out of 61 27%
Flops: 0
Latches: 0
Number of CLBs 9 out of 196 4%
Total Latches: 0 out of 392 0%
Total CLB Flops: 8 out of 392 2%
4 input LUTs: 16 out of 392 4%
3 input LUTs: 5 out of 196 2%
Number of BUFGLSs 1 out of 8 12%
Number of OSCILLATORs 1 out of 1 100%
Number of STARTUPs 1 out of 1 100%
5) What is the maximum net delay in the design? (See the Post Layout Timing Report.) What is the maximum clock frequency that can used for this design? What is the difference?
10.4ns
51.9Mhz
System clock frequency is limited by the slowest synchronous delay, and not necessarily by the slowest asynchronous net delay.
Timing summary:
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Design statistics:
Minimum period: 19.250ns (Maximum frequency: 51.948MHz)
Maximum net delay: 10.471ns