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Background Statement for SEMI Draft Document 5822A

New Standard,SPECIFICATION FOR REFERENCE MATERIAL FOR BONDED WAFER STACK VOID METROLOGY

Notice: This background statement is not part of the balloted item. It is provided solely to assist the recipient in reaching an informed decision based on the rationale of the activity that preceded the creation of this Document.

Notice: Recipients of this Document are invited to submit, with their comments, notification of any relevant patented technology or copyrighted items of which they are aware and to provide supporting documentation. In this context, “patented technology” is defined as technology for which a patent has issued or has been applied for. In the latter case, only publicly available information on the contents of the patent application is to be provided.

Background

The Guide for Measuring Voids in Bonded Wafer Stacks (SEMI 3D13) summarizes the state of the art in 2013/2014 for void detection. Going forward, a test sample of known void dimensions is needed for metrology system development and calibration. This Specification provides the details to create such a sample.

The ballot results will be reviewed and adjudicated at the meetings indicated in the table below. Please check Standards Calendar for the latest update.

Review and Adjudication Information

Task Force Review / Committee Adjudication
Group: / 3DS-IC Inspection and Metrology TF / 3DS-IC NA TC Chapter
Date: / July 12, 2017 / July 12, 2017
Time & Timezone: / 13:00 – 14:00 PDT / 15:00 – 17:00 PDT
Location: / San Francisco Marriott Marquis Hotel / San Francisco Marriott Marquis Hotel
City, State/Country: / San Francisco, California/USA / San Francisco, California/USA
Leader(s): / Steve Martell (Sonoscan) / Richard Allen (NIST)
Chris Moore (BayTech-Resor)
SeshRamaswami (AMAT)
Standards Staff: / Laura Nguyen () / Laura Nguyen ()

This meeting’s details are subject to change, and additional review sessions may be scheduled if necessary. Contact the task force leaders or Standards staff for confirmation.

Telephone and web information will be distributed to interested parties as the meeting date approaches. If you will not be able to attend these meetings in person but would like to participate by telephone/web, please contact Standards staff.

SEMI Draft Document 5822A

New Standard, SPECIFICATION FOR REFERENCE MATERIAL FOR BONDED WAFER STACK VOID METROLOGY

1 Purpose

1.1 A bonded waferreference sample of known void dimensions is needed for metrology system development and calibration. This Specification provides the details that shallbe used to create such a bonded wafer reference sample and is based on 300 mm reference samples used in a SEMI round robin study and published as SEMI AUX032-0715 – Round Robin Study of Method for Measurement of Voids in Bonded Pairs of Silicon Wafers.

2 Scope

2.1 This Specification describes requisite test structures, including design, manufacturing, and certification procedure for a bonded wafer reference sample composed of two wafers.

NOTICE:SEMI Standards and Safety Guidelines do not purport to address all safety issues associated with their use. It is the responsibility of the users of the documents to establish appropriate safety and health practices, and determine the applicability of regulatory or other limitations prior to use.

3 Limitations

3.1 The tools that are available to identify and measure the programmed voids after bonding that result from use of this Specification are not described in this document, but can be found in SEMI 3D13.

3.2 The potential and actual effects of bond voids on the performance and reliability of fabricated devices are not considered for this reference material specification.

3.3 The actual shape of the void trenches and the measurement technology used will affect the accuracy of the measurement(s).

3.4 This Document makes no determination of the usefulness of test structure in a stack of more than two wafers.

4 Referenced Standards and Documents

4.1 SEMI Standards and Safety Guidelines

SEMI 3D13– Guide for Measuring Voids in Bonded Wafer Stacks

SEMI AUX032-0715 – Round Robin Study of Method for Measurement of Voids in Bonded Pairs of Silicon Wafers

4.2 Other Documents

“Vision Measuring Systems Advance Noncontact Dimensional Measuring Technology”, Allen Cius, Quality Magazine, September 5, 2014.

NOTICE: Unless otherwise indicated, all documents cited shall be the latest published versions.

5 Terminology

5.1 Abbreviations and Acronyms

5.1.1 BWP — Bonded Wafer Pair

5.2 Definitions

5.2.1 capwafer — The top wafer of the Bonded Wafer Pair (BWP) that is typically unpatterned, i.e. not etched. If overlay fiducials are used in the bonding process the cap wafer shall have etched fiducials.

5.2.2 voidwafer — The bottom wafer of the Bonded Wafer Pair (BWP) that has been etched with the specified pattern to simulate voids.

6 Reference Test Specimen

6.1 The reference test specimen consists of two wafers – a patterned Void Wafer and an unpatterned Cap Wafer – that are bonded together to form a Bonded Wafer Pair (BWP). This reference test specimen includes die-sized arrays with sub-die regions with known void sizes and locations. The programmed bond voids are created by etching square wells in the Void Wafer of each BWP. The etched wells shall be patterned with openings ranging from 0.5 μm to 300 μm wide per the specified pattern, as shown in Figure 1. Threedifferent void patterns within each sub-dieshall be used: semi-dense,isolated,and dense, as shown in Figure 2. The Void Wafer shall be etched to a specified depth for the entire wafer, with recommended etch depths ranging from 4 nm to 1200 nm, as shown in Figure 3. In each BWP, the Cap Wafer shall be unpatterned.The bonding of the wafers, typically silicon,for BWP should be done using an oxide bonding process for silicon wafers and an equivalent process for wafers of other materials.

Figure 1
Layout of the Artificial Voids of Different Sizes and Densities in a Die-Sized Array

Figure 2
Details of the Arrangement of Artificial Voids at Different Densities (Not Drawn to Scale)

Figure 3
Schematic Diagram Showing Examples of Etched Wells Used to Produce Artificial Voids at the Bonded Interface Between Two Direct Bond Silicon Wafers

6.2 Die-Sized Arrays — LayoutDescription

6.2.1 As shown in Figure 1, each die-sized array consists of sub-die with void sizes from 0.5 μm to 300 μm wide per the specified pattern. The outer dimensions of each die-size array shall be 25 mm× 32 mm in the X and Y dimensions respectively. Each die-sized array may have an overlay fiducial located at its center.

6.2.2 Sub-Die — The sub-die for each void size consists of threedifferent void patterns within a sub-dieshall be used: semi-dense,isolated,and densewithin the specified pattern, as shown in Figure 2. Each sub-die region shall also include a void size label indicating the nominal size of the voids within that region.

6.2.3 Reference Voids — The artificial reference voids shall be etched into the Void Wafer with the specified semi-dense, isolated and dense voids of the same size for each sub-die region, as shown in Figures 1 and 2. Each void in a sub-die region shall be etched with a square pattern with each side of the square having the same dimension in the X andY orientations of the Void Wafer. Reference voids of the following dimensions (X andY) shall be etched; 0.5, 1.0, 2.5, 5.0, 10.0, 15.0, 25.0, 50.0, 75.0, 100.0, 125.0, 150.0, 175.0, 200.0, 225.0, 250.0, 275.0, and 300.0 µm. The tolerance of the etched reference 100µm void size shall be ±0.1 µm.

6.2.4 Void Etch Depth — The etch depth of the artificial reference void can be selected to help determine the sensitivity of an inspection technique to the Z dimension of a void, like is done for the X-Y dimensions. Since the nominal depth of etch is typically consistent over the entire Void Wafer it is common to select one etch of depth per wafer. The recommended etch nominal depths per Void Wafer are; 400, 200, 100 and 50 nm, based on the measured depth (Z) of the 100 µm void size in X and Y dimensions (See Note 1). The actual depth of the void shall be tracked by the Wafer ID of the Void Wafer.

6.2.4.1 The nominal etch depth shall be done by one of the following methods; Etching through the Silicon Dioxide (SiO2) layer and into the silicon of the Void wafer to the desired depth (See Note 2) or building up the Silicon Dioxide (SiO2) layer to a known thickness and etching through the oxide layer to the silicon (See Note 3).

  • Alternative void etch depths can be utilized as needed. The nominal depth of the void etched shall be tracked by the Wafer ID of the Void Wafer.
  • If void etch depths are varied for each die-array on a Void Wafer the nominal depth of the void etched shall be tracked by the Wafer ID and the Die Address (X = column # andY = row #) of the Void Wafer.
  • The actual thickness of artificial voids used in the original study at the nominal 40 nm voids ranged from 10 to 60 nm during tests run and published as SEMI 3D13 and SEMI AUX032-0715. The depth of etch shall be tracked by the Wafer ID of the Void Wafer.
  • The actual etch depth will vary depending on the feature size being etched and the spatial uniformity of the etch tool. As a reference, the 100 µm void size in X and Y dimensions shall be used for measuring the etch depth to determine the nominal etch depth for that wafer.
  • The thickness of a Silicon Dioxide (SiO2) layer can typically be controlled to ±5% of the desired thickness of 500 Å to 15μm.
  • Bonded Wafer Stack — Layout Description

Figure 4
Example layout of the die-sized arrays with artificial voids of different sizes and densities in a Bonded Wafer Pair (BWP). This example is for a 300mm diameter wafer and also shows the recommended numbering system for the die-sized arrays

6.3.1 The reference test specimen consists of two wafers that are bonded together, called a Bonded Wafer Pair (BWP) to form a reference test structure with die-sized arrays with known sub-die void sizes and locations. Two wafers of same or different materials are bonded together. The etched Void Wafer, shown in Figure 3, is typically silicon. The Cap Wafer is typically silicon or glass.

6.3.2 Void Wafer — The void wafer exhibits an indented pattern that is typically created by etching away the undesired wafer material to the pattern, shown in Figure 1, for each die-sized array. Typically for silicon wafers that are directly bonded the oxide layer on each of the wafers, as shown in Figure 3. If the oxide layer is being used to establish the void etch depth desired it shall be uniform with the tolerance of ±5% of the thickness (void depth) desired. The mask for this pattern is available through SEMI via a download with the purchase of this standard from SEMI.

6.3.3 Cap Wafer — The cap wafer is flat and typically unpatterned. Therefore, the bonded area between the wafers is limited to the regions outside of the patterned, die-size arrays etched into the void wafer, as seen in Figures 1 and 4.

6.3.4 Bonded Wafer Process – Different wafer bonding techniques are employed to bond the wafers together. It is this technique that ultimately determines the quality and strength of the bonded wafer pair. This specification does not recommend bonding techniques; rather, it is used as a vehicle to ascertain the wafer bond quality and void detection capabilities of different inspection techniques.

6.3.5 Wafer Sizes — The size of the example BWP shown in Figure 4 is 300mm with the Die-size Array Layout of 9 columns × 7 rows. Other wafer sizes with scaled down layouts can be used. Provided below is the recommended die-size array layouts for selected BWP sizes.

  • 300mm (12 in.) Wafers: 9 columns × 7 rows
  • 200mm (8 in.) Wafers: 7 columns × 5 rows
  • 150mm (6 in.) Wafers: 5 columns × 3 rows
  • 100mm (4 in.) Wafers: 3 columns × 3 rows

7 Ordering Information

7.1 Mask Pattern — Mask for this pattern is available through SEMI via a download with the purchase of this standard from SEMI.

8 Certification Dimensional Measurements

8.1 Reference void dimensions shall be measured on the Void Wafer prior to bonding to certify the BWP. The following procedure shall be used to determine the actual dimensions; XandY and depth etch Z, for a random sampling of 100 µm size voids per each BWP. The X and Y dimensional measurements shall be done with an accuracy of 0.1 µm at minimum. The depth etches Z dimensional measurement shall be done with accuracy relevant to the measurement technique utilized per section 8.3 and documented.

8.2 Die site selection — Selection of three die-size arrays for measurement shall be done by randomly choosing one die-size array along the center row (±X,0), the secondfrom the row(s) above the center line (±X,+X), and the third from the row(s) below the center line (±X,-X). The location of the three die-size arrays chosen shall be documented.

8.3 Required Dimensional Measurement — Selection of 11 “100 µm” size voids for measurement shall be done by randomly choosing five “100 µm” voids in the semi-dense region and five “100 µm” voids in the dense region, plus the oneisolated void for a total of 11 void measurements per chosen die-size array. The five “100 µm” voids measured within the semi-dense and dense regions shall be chosen by selecting one void near the vertical centerline and two voids each above and below the centerline. The “100 µm” voids selected shall have their location documented as semi-dense, isolated or dense region, and the column # and row# for the voids within the semi-dense and dense regions. The 0,0 point for the column and row numbers shall start at the lowest left void in the pattern.

8.4 Additional Dimensional Measurements — Actual void dimensions for void sizes other than “100 µm” size voids shall be done for two other void sizes to quantify variation. One void size above and one void size below “100 µm” shall be chosen for these measurements. The selection of the die-size arrays and voids for measurement shall follow the same procedures outlined in sections 8.1 and 8.1, respectively, for the void sizes chosen.

8.5 Measurement Techniques — Depending on the material(s) and structure of the Void Wafer one or more of the following measurement techniques can be used. The actual measurement technique used shall be documented.

8.5.1 X-Y Dimensions — Some form of noncontact measurement shall be used with a minimum measurement accuracy of 0.1 µm in the XandY dimensions. A noncontact measurement technique is recommended over a contact technique to limit potential contamination of the bond surface and to retain the edge shape of the etched voids. There are a variety of noncontact dimensional measurement techniques and systems that can be utilized to measure the actual size (Xand Y) of the voids formed in the Void Wafer.Some of the recommended techniques are, but not limited to the following; Confocal, White light interferometry (WLI), Camera, Optical and Scanning lasers. [“Vision Measuring Systems Advance Noncontact Dimensional Measuring Technology”, Quality Magazine, September 5, 2014].

8.5.2 Z Dimension — Some form of noncontact measurement should be used with a minimum measurement accuracy of 10.0 nm in the Z dimension. A noncontact measurement technique is recommended over a contact technique to limit potential contamination of the bond surface and to retain the edge shape of the etched voids. There are a variety of noncontact dimensional measurement techniques and systems that can be utilized to measure the actual etch depth (Z) of the voids formed in the Void Wafer. Some of the recommended techniques are, but not limited to the following; Confocal, White light interferometry (WLI), Camera, Optical and Scanning lasers.

  • As an alternative when a known thickness of oxide layer is applied and will be etched to the silicon for the Z depth desired, a visual technique may be utilized to determine if the oxide layer has been etched through for the “100 µm” voids randomly selected as per section 8.1. The measurement of the depth etch shall then be documented based on the oxide known thickness and tolerance.

9 Certification

9.1 Documentation — Manufacturer of the BWP shall provide a certificate with its contact information, i.e. letter head, with each BWP that contains the following information at minimum, so the data provided can be used as a known reference by the user of the BWP.

9.1.1 Wafer Materials and Sizes — Wafers’ bulk material (i.e. Silicon) and nominal diameter (i.e. 300 mm) for:

9.1.1.1 Void Wafer

9.1.1.2 Cap Wafer

9.1.2 Wafer Identifications — Wafer markings per section 10.1 for:

9.1.2.1 Void Wafer

9.1.2.2 Cap Wafer

9.1.2.3 Bonded Wafer Pair (BWP)

9.1.3 Voids Etched into Void Wafer — Void measurements made as per sections 8.1 and 8.2 for:

9.1.3.1 100 µm voids

  • Location of the three die-size arrays chosen
  • Location of the 11 100 µm voids chosen (five semi-dense, isolated and five dense) per dies-size array
  • Actual XandY measurement of the 100 µm voids chosen
  • Actual Z depth measurement of the 100 µm voids chosen
  • List of equipment and the calibration standard(s) used for each measurement
  • One void size less than 100 µm
  • Nominal size (X µm) of the void size chosen less than 100 µm
  • Location of the three die-size arrays chosen
  • Location of the 11 voids (X µm) chosen (five semi-dense, isolated andfive dense) per dies-size array
  • Actual X andY measurement of the voids (X µm) chosen
  • Actual Z depth measurement of the voids (X µm) chosen
  • List of equipment and the calibration standard(s) used for each measurement
  • One void size greater than 100 µm
  • Nominal size (X µm) of the void size chosen greater than 100 µm
  • Location of the three die-size arrays chosen
  • Location of the 11 voids (X µm) chosen (five semi-dense, isolated and five dense) per dies-size array
  • Actual XandY measurement of the voids (X µm) chosen
  • Actual Z depth measurement of the voids (X µm) chosen
  • List of equipment and the calibration standard(s) used for each measurement

10 Product Labeling