ASIC Design Using Organic Transistors

ASIC Design using Organic Transistors

Submitted in partial fulfillment of the requirements

of the degree of

Doctor of Philosophy

by

RameshRajuNavan

(Roll No. 05407009)

Supervisors:

Prof. V. RamgopalRao

Prof. M. ShojaeiBaghini

Department of Electrical Engineering

Indian Institute of Technology Bombay, Mumbai

(2012)

Abstract

This report summarizes thefabrication, characterization, mobility enhancement and development of a novel device and circuit simulation technique for organic thin film transistors (OTFTs). In this work we have mainly studied solution processed poly (3-hexylthiophene) (P3HT) and vacuum evaporated pentacenebased p-type OTFTs.

The first part of the work is focused on the mobility enhancement of OTFTs.Several methods of dielectric surface treatments were found favorable for organic layer and they were compared with each other. A novel procedure for octadecyltrichlorosilane (OTS) deposition was explored and verified experimentally to give improved mobility of pentacene OTFTs. OTS deposition on silicon dioxide and hafnium oxide were found to give better mobility compared to other methods tried.We also demonstrated mobility enhancement of P3HT p-type of organic transistors by dispersing Zinc Oxide (ZnO) nanostructures into it. A comparative picture is presented between these composite based and pristine P3HT transistors. Our results indicatesmore than 60%mobility enhancement in the composite transistors compared to pristine ones.However, there is still scope for further improvement in terms of better dispersion of ZnO nanostructures.

Due to lack of compact models for OTFTs we have used alternate approaches to perform device and circuit simulations of OTFTs and they are discussed as second part of the work. One approach of circuit simulation of OTFTs was to extract equivalent SPICE (Simulation Program with Integrated Circuit Emphasis) parameters of OTFTs with the help of particle swarm optimization (PSO) algorithm. The extracted equivalent SPICE parameters are used as a device model for SPICE based circuit simulations. Another approach for OTFT device simulation was done by use of ISE-TCAD (Integrated Systems Engineering - Technology Computer Aided Design) in it the device parameters for silicon were replaced by those of organic semiconductor. The results obtained from device simulation procedure were then used to generate the Look-up Tables (LUTs) of the organic devices. LUT of the OTFT can also be directly obtained from the experimental data. LUT generated is used as a model file in SEQUEL (Solver for circuit EQuations with User-defined ELements) for simulating circuits. Simulated results were verified experimentally.

The third part deals with the fabrication and optimization of gate dielectrics. Here we have demonstrated organic field effect transistors (OFETs) with photo-patternable, solution processed,nanoparticle composite high-k gate dielectric layer. The dielectric layer consists of Barium Titanate (BT) nanoparticles dispersed in SU-8, which makes it possible to use solution-processable methods. The dielectric constant k of the nanoparticle composite films can be tuned over a wide range by varying the concentration of BT particles, which enables lower voltage operation possible with these composite gate dielectric films. OFETs with P3HT as the semiconducting layer have been demonstrated; it was found that the OFETs with the nanocomposite dielectric layer show a significant improvement in the drive current yet retaining the photopatternability, which is an advantage for circuit fabrication. The composite being a high-k enables low voltage operation (∼4V) compared to pristine SU-8 as a gate dielectric operating at high voltages (∼40V). Working organic transistors and inverters with a high-k nanocomposite dielectric layer (k13) with considerably lower leakage current have been demonstrated.

In the last part, a new compact OTFT-based analog to digital converter(ADC)was designed and simulated using LUTbased approach in SEQUEL circuit simulator.The LUT data was obtained from fabricated P3HT-based OTFTs with the developed high-k photopatternablegate dielectric layer. The LUT simulation approach was validated at the circuit level using the measurements taken on fabricated OTFT-based inverter. With the limitation in yield and stability of P3HT-based components circuit modules were designed with fewer transistors.Designing a differential architecture makes it less sensitive to variation of threshold voltage of input transistors. Theproposeddesign and circuitsimulationresults show a great promise for simulation and complex designing approach advantageous for different organic electronic applications.

Keywords- organic semiconductors,OTFT, pentacene, P3HT, HfOx,SAM, ZnO, OTFT circuit simulation,signal conditioning, analog to digital converter.

Contents

Abstract / ii
List of Figures / vi
List of Tables / xii
Abbreviation and Nomenclature / xiii
1 / Introduction / 1
1.1 Organic Semiconducting Materials / 3
1.2 Conduction Mechanisms / 4
1.3 OTFT Device Structure and Model / 5
1.4 Circuit Simulation of OTFTs / 8
1.5 Overview of the Thesis / 9
2 / Organic Thin Film Transistors Performance Parameters / 12
2.1 Introduction / 12
2.2 Factors Affecting Mobility / 15
2.2.1 Deposition Process / 15
2.2.2 Temperature / 16
2.2.3 Charge Trappings in Polymer / 16
2.2.4 Influence of Structural Imperfections in Polymer / 17
2.2.5 Surface Modification Technique - SAM / 18
2.2.6 Mobility Enhancement of Pentacene OTFT using SAM / 23
2.2.7 Mobility Enhancement of P3HT OTFT using ZnO Nanostructures / 34
2.3 Controlling Threshold Voltage / 45
2.3.1 Factors affecting Threshold Voltage / 46
2.3.2 Metal Work Function Tuning / 48
2.3.3 Double Gate Structures / 48
2.3.4 Self Assembled Monolayer / 49
2.3.5 Deliberate Interface Trap Creation / 50
2.3.6 Threshold Voltage Tuning of Pentacene OTFTs using SAM / 50
2.4 Conclusion / 59
3 / Fabrication and Simulation of P3HT and Pentacene OTFT and Circuits / 60
3.1 Introduction / 60
3.2 P3HT OTFT Devices and Inverters / 61
3.2.1 Fabrication and Characterization / 61
3.2.2 OTFT Simulation using SPICE / 65
3.2.3 Results and Discussions / 65
3.3 Pentacene OTFT Devices and Inverters / 66
3.3.1 Fabrication and Characterization / 66
3.3.2 OTFT Simulation using LUT based Approach / 70
3.3.3 Results and Discussions / 73
3.4 Circuit Design Methodology / 78
3.4.1 Circuit Design Problems with OTFT Technology / 79
3.4.2 Bootstrap Inverter / 79
3.4.3 Bootstrapped Circuit Simulation / 80
3.4.4 Bootstrapped Circuit Fabrication / 83
3.5 Conclusion / 85
4 / Optimization of the Gate Dielectric / 87
4.1 Introduction / 87
4.2 Fabrication Procedure / 87
4.3 Characterization Results / 88
4.3.1 Silicon Nitride as Gate Dielectric / 89
4.3.2 Hafnium Oxide as Gate Dielectric / 89
4.3.3 Stacked Hafnium Oxide/Silicon Dioxideas gate dielectric / 90
4.3.4 PMMA as Gate Dielectric / 90
4.4 A Novel High-k (k > 40) Gate Dielectric / 91
4.4.1 Introduction / 91
4.4.2 Experiment / 91
4.4.3 Results and Discussion / 92
4.5 Solution Processed Photopatternable High-k NanocompositeGate Dielectric / 93
4.5.1 Introduction / 93
4.5.2 Experiment / 95
4.6 Conclusion / 100
5 / OTFT Circuit Design and Simulation for Signal Conditioning Application / 101
5.1 Introduction / 101
5.2 Signal Conditioning Circuit / 102
5.2.1 LUT based Simulation of High-k OTFT Device and Inverter Circuit / 105
5.2.2Analog to Digital Converter Design / 107
5.3 Conclusion / 110
6 / Summary and Future Work / 111
References / 115
List of Publications / 126

List of Figures

1.1 / OTFT device configurations: (1) Bottom gate (a) Top-contact device (b) Bottom-contact device (2) Top-gate……………………………………...... / 6
1.2 / Structure of an all polymer transistor where source, drain and gate were printed by inkjet technique, semiconducting and insulating layers were spin coated/inkjet printed………………………………………………...... / 6
1.3 / General flow showing optimized device fabrication steps and OTFT circuit simulation approach…………………………………………………………….. / 9
1.4 / Illustration of the organization of the thesis……………………………...... / 11
2.1 / Typical electrical characteristic of a p-channel OTFT device: (a) Output curve and (b) transfer curve…………………………………………………………… / 13
2.2 / Relation between grain size and mobility…….………………………………… / 18
2.3 / Formation of SAM on SiO2…...………………………………………………... / 19
2.4 / Octadecyltrichlorosilane structure…………………………………………….... / 20
2.5 / Hexamethyldisilazane structure………………………………………………… / 21
2.6 / Porphine structure……….……………………………………………………… / 21
2.7 / 5-(4-Hydroxyphenyl)-10, 15, 20-tri (p-tolyl) porphyrin………………………... / 22
2.8 / Surface characterization based on contact angle measurements………………... / 23
2.9 / Formation of hydroxyl phenyl porphyrin SAM on SiO2……………………….. / 26
2.10 / AFM surface images of (a) baresilicon dioxide (SiO2) surface (b) HMDS SAM on SiO2 (c) OTS SAM on SiO2 (d) Piranha + OTS SAM on SiO2………. / 27
2.11 / Top-contact bottom-gate OTFT structure………………………………………. / 28
2.12 / Comparison plots with and without SAM……………………………………… / 29
2.13 / Top-contact bottom-gate OTFT structure………………………………………. / 31
2.14 / Comparison plots with and without SAM……………………………………… / 32
2.15 / Schematic of all-p type organic inverter with enhancement mode driver (M1) and Load (M2) and inverter cross-sectional view………………………………. / 33
2.16 / Inverter DC characteristics (VDD = 4 V) of organic inverter with and without OTS SAM on sputtered HfOxas gate dielectric and dimensions (W/L)M1= 24850 μm/50 μm and (W/L)M2 = 5050 μm/50 μm, respectively………………... / 34
2.17 / Vapor-Liquid-Solid apparatus used for the growth of zinc oxidenanostructures…………………………………………………………………... / 36
2.18 / Scanning electron micrographs of the wool-like structures grown in the high temperature zone in a Vapor Liquid-Solid (VLS) Process……………………... / 36
2.19 / Cross-sectional view of the P3HT/ZnOnanocomposite transistor considered in this work………………………………………………………………………... / 38
2.20 / Comparison of typical (a) output characteristics, gate voltage is different for each curve, varied from 0V to -40V in steps of -5V (b) transfer characteristics, drain Voltage is -40V of transistors based on pristine P3HT and ZnO/P3HT composite transistors…………………………………………... / 38
2.21 / (a) SEM and (b) TEM images of ZnOnanorods grown for 1.5 h by a simple one-step chemical approach. A SAED pattern of ZnOnanorods is shown as the insets of the TEM images…...... / 40
2.22 / (a) Cross-sectional view of the P3HT/ZnOnanocompositebased bottom contact organic field effect transistor. (b) Transfer (IDS-VGS) characteristics comparison for different concentration of ZnOnanorods in P3HT/ZnOnanocomposite where VGS is varied from +10 to -40 V & VDS = -40 V (c) Output (IDS-VDS) characteristics of pristine P3HT devices. Similarly (d) to (f) show the output characteristics for 0.5 mg, 1 mg & 1.5 mg ZnOnanorods dispersed in a 1.5 mg of P3HT in chloroform solution where VDS is varied from 0 to -40 V & VGS varied from 0 to -40 V in steps of -10 V, respectively (W/L = 24300 µm /65 µm)……………………………………………………... / 42
2.23 / Statistically analyzed mobility data of pure and P3HT/ZnO (different ZnO weight %) nanocomposite. The observed increase in mobility is mainly due to the reduction of traps in P3HT………………………………………………….. / 43
2.24 / SEM image of ZnOnanorods (sample (a), sample (b) and sample (c))………... / 44
2.25 / XRD patterns of ZnOnanorods (sample (a), sample (b) and sample (c))……… / 44
2.26 / Transfer (IDS-VGS) characteristics comparison for different aspect ratios of ZnOnanorods in P3HT/ZnOnanocomposite. Here, VGS is varied from +10 to -30 V & VDS = -30 V for aspect ratio of 15, 25 & 60 ZnOnanorods dispersed in a 1.5 mg of P3HT in chloroform solution, respectively (W/L = 24000 µm/50 µm)………………………………………………………………………...... / 45
2.27 / Threshold voltage dependence on polymer thickness [71]……………………... / 46
2.28 / Change in threshold voltage with temperature [30]…………………………….. / 47
2.29 / Drain current vs. gate voltage stress [30]……………………………………….. / 47
2.30 / Device geometry of dual gate structure [72]……………………………………. / 48
2.31 / Threshold voltage vs. top-gate voltage [72]…………………………………… / 48
2.32 / Drain current vs. gate voltage curves with and without OTS treatments [73]….. / 49
2.33 / Threshold Voltage vs. exposure time of treatment [75]………………………... / 50
2.34 / AFM surface images (a) SiO2 (b) Porphyrin SAM on SiO2 [35]……………….. / 52
2.35 / UV-Vis spectrum of porphyrin in toluene and and SAM on SiO2 [35]………… / 53
2.36 / Structure of OFET with SAM layer…………………………………………….. / 53
2.37 / Log |IDS|-VGS curve for OFET with W = 4186 μm and L = 100 μm for oxide thickness of 100 nm ……………………………………………………………. / 54
2.38 / Log |IDS| vs. VGS plot for devices with Al2O3 as dielectric and W=2000 µm and L=150 µm…………………………………………………………………. / 54
2.39 / AFM images of (a) pentacene on Al2O3 and (b) pentacene on SAM on Al2O3… / 57
2.40 / Id-Vg characteristics of OFET with and without SAM (copperporphyrin)……. / 58
2.41 / FTIR results of samples before and after plasma exposure…………………….. / 58
3.1 / OTFT structure in Bottom Gate Bottom contact configuration with patternedgate (Al)…………………………………………………………………...... / 61
3.2 / Output (IDS-VDS), characteristics of a typical fabricated OTFT with HfOx as gate dielectric.…………………………………………………………………... / 62
3.3 / IDS-VGS (triangles) and IDS1/2 -VGS (solid line) plots of OTFT with HfOx gate dielectric (W/L=15200µm/20 µm)…………………………………………… / 62
3.4 / Schematic of all-p type organic inverter with enhancement mode driver (M1) and load (M2).…………………………………………………………………. / 63
3.5 / DC transfer characteristics of an organic inverter with (W /L)M1= 8400 µm/100 µm and (W/L) M2 = 2150µm/100µm………………………………….. / 64
3.6 / Measured transient characteristics of organic inverter. The transient delays are estimated to be roughly 10 ms………………………………………………….. / 64
3.7 / Comparison of measured vs. simulated IDS − VDScharacteristics OTFTs ……... / 66
3.8 / Cross-section of the patterned gate fabricated OTFT…………………………... / 67
3.9 / Patterened gate OTFT with sputtered-SiOx (60nm) as gate dielectric and patterned pentacene as semiconducting material. ….…………………………... / 67
3.10 / Schematic of all-p type organic inverter with enhancement mode driver (M1) and load (M2) and inverter cross-sectional view…….………………………… / 68
3.11 / The measured DC and transient characteristics of an inverter with (W/L)M1=24850 μm/50 μm and (W/L)M2= 3550 μm/50 μm.……………………………... / 68
3.12 / Output characteristics withsputtered-HfOx (45nm) as gate dielectric…………. / 69
3.13 / The measured DC and transient characteristics of an inverter with (W/L)M1= 24850 μm/50 μm and (W/L) M2 = 5050 μm/50 μm…………………………….. / 69
3.14 / Patterened gate OTFT with sputtered HfOX (65nm) as gate dielectric and patterned pentacene as semiconducting material with (W/L) = 24850 μm/50μm / 70
3.15 / The measured DC and transient characteristics of an inverter with (W/L) M1 = 24850 μm/50 μm and (W/L) M2= 5050 μm/50 μm……………………………… / 70
3.16 / Cross-section of a bottom contact OTFT device drawn in MDRAW (ISE-TCAD tool) (a) before meshing (b) after meshing of the device……………… / 72
3.17 / Measured vs. simulated ID − VD characteristics for OTFTs fabricated (data scaled to width W=1μm)…………………………………………………...... / 74
3.18 / (a) DC transfer characteristics and (b) transient response of the simulated all p-type enhancement mode organic inverter for VDD = 5 V. Inset shows the schematic of Inverter……. …………………………………………………… / 75
3.19 / (a) Two input NAND gate with only p-type transistors gate(b) simulated characteristics…………………………………………………………………… / 76
3.20 / (a) Two input NOR gate with only p-type transistors gate(b) simulated characteristics…………………………………………………………………… / 76
3.21 / Output characteristics of a 5-stage simulated ring oscillator…………………… / 77
3.22 / Measured vs. simulated output characteristics for OTFTs……………………... / 77
3.23 / (a) P-type OTFT inverter and (b) Transient response of the simulated p-type enhancement-mode organic inverter for VDD = 4 V……………………………. / 78
3.24 / Bootstrapped inverter.…………………………………………………………... / 79
3.25 / Comparison of measured vs. simulated IDS − VDScharacteristics OTFTs (W/L=500μm/150μm)…………………………………………………………...... / 81
3.26 / Shows the results of transient simulation of p-type basedinverter circuit and p-type bootstrapped inverter……………………………………………………… / 81
3.27 / Shows the p-type based dynamic logic circuit(a) without and (b) with bootstrap technique……………………………………………………………... / 82
3.28 / Plots for p-type dynamic logic inverter with and without bootstrapping………. / 82
3.29 / (a) The schematic of bootstrap inverter circuit, (b) SEM picture of fabricated bootstrap inverter. (c) DC transfer characteristics of a fabricated bootstrapped organic inverter. The sweep rate of the input for DC characteristics of inverter is 0.1V/s. The dashed curve shows the output for a normal inverter with identical transistors, (d) The transient response of the normal inverter and (e) The transient response of the bootstrapped inverter [82]……………………….. / 85
4.1 / Bottom-gate top-contact OTFT using BDFO as gate dielectric………………... / 91
4.2 / Transistor characteristics (a) drain current (ID) versus drain-source voltage (VDS) (b) drain current (IDS) versus gate voltage (VGS) of the OTFT with BDFO as the gate dielectric…………………………………………………………….. / 93
4.3 / Effect of BT wt% on the thickness of the spin coated composite film.(Inset shows the structure of the MOS capacitor)……………………………………... / 96
4.4 / (a) Capacitance verses frequency plots for different concentration of BT nanoparticles blended into the SU-8 dielectric films and (b) dependence of resistivity and dielectric constant on BT wt%...... / 96
4.5 / (a) Schematic cross-section of bottom contact organic field effect transistor with a nanocomposite gate dielectric (b) & (c) transfer (IDS-VGS)output (IDS-VDS) characteristics of pristine SU-8 gate dielectric, and (d) &(e) transferoutput characteristics of composite SU-8 with 0.88 BT wt% gate dielectric (W/L=24000µm/50µm)……………………………………………………….. / 97
4.6 / Shows AFM images of (a) pristine SU-8 and (b) 0.88 BT wt% in SU-8/BT nanocomposite………………………………………………………………….. / 98
4.7 / (a) Cross-sectional structure of the organic inverter after semiconductor layer formation (b) Schematic of all p-type organic inverter with enhancement mode driver (M1) and Load (M2), and (c) DC transfer characteristics of a typical organic inverter…………………………………………………………………. / 99
5.1 / Signal conditioning block diagram……………………………………………... / 102
5.2 / Schematic cross-section of a bottom-gate-bottom contact p-type OFET with P3HT as its active material [122].…………...... / 102
5.3 / Response of the OFET with radiation.………………………………………….. / 103
5.4 / Emulated radiation sensor and its result by simulation………………………… / 103
5.5 / Transimpedance amplifier (TIA) with sensor block and its response………….. / 104
5.6 / (a) Cross-section of OTFT device (b) measured vs. LUT simulated output characteristics for OTFTs………………………………………………………. / 106
5.7 / (a) P-type OTFT inverter and (b) transient response of the simulated p-type enhancement-mode organic inverter for VDD = 4 V……………………………. / 107
5.8 / (a) Differential inverter circuit using four p-type transistors (b) LUT-based simulation results of the switching characteristic of the inverter for higher values of VIN, the output voltage tends to saturate to the threshold voltage of M2………………………………………………………………………………. / 108
5.9 / Block diagram of the ADC circuit synthesized using the voltage divider and the differential inverter circuit………………………………………………….. / 109
5.10 / (a) Cascade circuit of a differential and simple inverter for each single bit of ADC (b) simulation results of the ADC………………………………………... / 109

List of Tables

2.1 / Parameter comparison for different conducting polymers……...... / 15
2.2 / Contact angle values after different surface treatments on SiO2 samples……………………………………………………………. / 26
2.3 / Roughness measurements after different surface treatments……... / 28
2.4 / Mobility and threshold voltage comparison after different surface treatments…………………………………………………………. / 30
2.5 / Contact angle values and roughness measurements after different surface treatments on HfOxsamples………………………………. / 31
2.6 / Mobility, threshold voltage and Ion/Ioff ratio comparison after surface treatment………………………………………………….. / 33
2.7 / Summary of comparative study of transistors based on pristine P3HT and P3HT/ZnOnanocomposites…………………………… / 39
2.8 / Roughness measurements after porphyrinSAM treatment [35]….. / 52
2.9 / Various parameters for different device structures……………….. / 56
3.1 / Measured parameters for the fabricated devicewith HfOx as gate dielectric…………………………………………………………... / 63
3.2 / SPICE parameters extractedextracted for P3HT OTFT………….. / 66
3.3 / Measured parameters forthe fabricated device with SiOxas gate dielectric…………………………………………………………... / 67
3.4 / Measured parameters for the fabricated device………………….... / 69
3.5 / Material parameters for pentacenesemiconductor [97]…………... / 73
3.6 / Defects location and density in pentacenefilms. All defects are Gaussian and acceptor type. Location is w.r.t. valence band [97].. / 73
3.7 / Device dimensions and measured parameters of the device……… / 74
3.8 / Spice parameters extracted after matching…………………...... / 74
3.9 / Device related parameters byexperiment………………………… / 80
3.10 / SPICE parameters extracted after matching………………………. / 80
4.1 / Summary of dielectric optimization……………………………..... / 90

Abbreviations and Nomenclature

ADC / -Analog to Digital Converter
AFM / -Atomic Force Microscopy
Al2O3 / -Aluminum oxide
Al / -Aluminium
Au / -Gold
BDFO / -Bi0.7Dy0.3FeO3
BEOL / -Back End Of Line
BGBC / -Bottom Gate Bottom Contact
BGTC / -Bottom-Gate Top-Contact
BT / -BariumTitanate
CNT / -Carbon Nanotubes
Cr / -Chromium
CuPc / -Copper phthalocyanine
CV / -Capacitance-Voltage
FTIR / -Fourier Transform Infrared Spectroscopy
HfOx / -Hafnium oxide
HMDS / -Hexamethyldisilazane.
HMTA / -Hexamethylenetetramine
HOMO / -Highest Occupied Molecular Orbital
ICPCVD / -Inductively Coupled Plasma Chemical Vapor Deposition
IGFET / -Insulated Gate Field-Effect Transistor
IPA / -Isopropyl Alcohol
ITO / -Indium Tin Oxide
IV / -Current-Voltage
LPCVD / -Low-Pressure Chemical Vapor Deposition
LUMO / -Lowest Unoccupied Molecular Orbital
LUT / -Look-up Table
MIS / -Metal Insulator Semiconductor
MOS / -Metal Oxide Semiconductor
MOCVD / -Metalorganic Chemical Vapor Deposition
MTR / -Multiple Traps and Release
NTCDA / -1,4,5,8-naphthalene tetracarboxylicdianhydride
NTCDI / -1,4,5,8-naphthalene tetracarboxylicdiimide
OFET / -Organic Field EffectTransistors
OLED / -Organic Light Emitting Diodes
OPVD / -Organic Photovoltaic Diodes
OTFT / -Organic Thin Film Transistors
OTS / -Octadecyltrichlorosilane
P3HT / -poly (3-hexylthiophene)
PEB / -Post exposure bake
PLD / -Pulsed Laser Deposition
PMMA / -PolymethylMethacrylate
PSO / -Particle Swarm Optimization
PTCDA / -PerlenetetracarboxylicDianhydride
PVD / -Physical Vapor Deposition
RCA / -Radio Corporation of America
RFID / - Radio-frequency identification
RT / - Room temperature
RTA / - Rapid Thermal Annealing
S / - Subthreshold Swing
SAED / - Selected Area Electron Diffraction
SAM / - Self-Assembled Monolayer
SEM / - Scanning Electron Micrographs
SiNx / - Silicon Nitride
SEQUEL / - Solver for circuit EQuations with User-defined Elements
SiO2 / - Silicon dioxide
SPICE / - Simulation Program with Integrated Circuit Emphasis
TCNNQ / - 11,11,12,12-tetracyanonaphtho-2,6-quinodimethane
TDEAH / - TetrakisDiethylamidoHafnium
TEM / - Transmission Electron Microscope
TGBC / - Top-Gate Bottom-Contact
Ti / - Titanium
TIA / - TransimpedanceAmplifier
VLS / - Vapor-Liquid-Solid
VRH / -Variable Range Hopping
XRD / -X-Ray Diffraction
VLSI / -Very Large Scale Integration
UV-Vis / -Ultraviolet-Visible
ZnCl3 / -Zinc Chloride
ZnO / -Zinc Oxide
μ / -Mobility
COX / -Gate Oxide Capacitance
W / -Channel Width
L / -Channel Length
IDS / -Drain source current
VGS / - Gate Source Voltage
VDS / - Drain Source Voltage
VT / -Threshold Voltage
VTO / -Turn-on/onset Voltage
VIN / -Input voltage of inverter
VOUT / -Output voltage of inverter
VDD / - Supply Voltage of inverter

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