Are ASIC Design Starts Tapering Off?
Over the last few years, the number of custom application-specific integrated circuits (ASICs) developed by companies has decreased several percentage points each year. This year, Bryan Lewis--the ASIC Industry Analyst at the Gartner Group/Dataquest in San Jose, Calif.--projects a decrease of 6.4% versus last year. That year had just over 3600 design starts (see Figure 1). By world region, Lewis sees the number of design starts remaining fairly consistent over the 2004-to-2005 timeframe. A 1% decrease in the percentage is attributed to the Americas and Japan. A 2% increase is attributed to the Asia-Pacific region, as more companies in that region are crafting their own ASIC solutions (see Figure 2).
According to Lewis, the decrease in design starts can be attributed to several factors. First of all, field-programmable gate arrays (FPGAs) offer higher levels of integration as well as lower price points. As a result, they continue to eat away at the number of digital ASIC design starts at the lower end of the ASIC market. Secondly, the cost to implement an ASIC is escalating as designs move from 130 to 90 nm and 90 to 65 nm process nodes. The number of companies that can afford to leverage the smaller feature sizes is therefore limited. Finally, companies are being more selective regarding which projects to move from concept to implementation. The speculative designs done in the late 1990s before the dot-com bubble burst have basically disappeared. Instead, companies are taking very hard looks at how they are spending their development funds.
The one exception to the negative number of design starts is in the area of mixed-signal ASICs. Because these chips include a significant amount of analog circuitry, they’re holding their own. Most FPGAs don’t offer much analog functionality. Yet that is changing as FPGAs incorporate analog phase-locked loops and high-speed, multi-gigabit-per-second serializer-deserializer (SERDES) ports. The latest challenge for mixed-signal ASICs is coming from Actel Corp. (Mountain View, CA). Its Fusion series of mixed-signal FPGAs combines high-density FPGA logic and configurable analog building blocks. Prior to the Fusion family, Cypress Semiconductor (San Jose, CA) and Lattice Semiconductor (Hillsboro, OR) both developed some low-complexity, programmable mixed-signal products that are used in consumer and industrial applications.
Depending on how the numbers are collected, they can deliver a different view of the number of design starts, emphasizes Richard Wawrzyniak, Senior Analyst for ASICs at Semico Research Corp. (Phoenix, AZ). Wawrzyniak feels that quarterly numbers don’t really provide an accurate view of the number of design starts. As a result, he prefers to look at yearly results. According to the numbers collected by Semico, there is a small percentage increase in the number of ASIC design starts. Mixed-signal devices are up while full-analog ASICs are flat. Structured ASICs, value systems-on-a-chip, and programmable-logic-based designs are all showing some growth.
Designs have shifted from 180 to 130 nm. As new designs at 180 nm begin to taper off, the number of 130-nm-based designs has increased. Wawrzyniak expects that the number of design starts at 130 nm may be hitting their peak in the next year or two. Interest is now starting to shift to the 90-nm process node for increased density and speed as well as lower power. There’s very strong consumer interest at the 90-nm process node because designers can achieve high levels of integration. With various process options, they also can optimize their designs for maximizing performance (if throughput is the critical issue) or low power (if long battery life is a key concern).
Today, low-cost FPGAs are available with capacities of about 1 million gates for less than $10 apiece in large quantities. At that price point, Wawrzyniak sees them being able to compete with lower-cost ASICs. After all, there are no major non-recurring-engineering (NRE) fees or mask sets. Plus, turnaround time (time to market) for a design (from product definition to manufacturing release) is much shorter--typically three to six months for an FPGA-based solution versus six to eight months for a structured-ASIC implementation and possibly 12 to 16 months for a full ASIC.
With FPGAs, designers also can easily modify the configuration pattern to add a feature or fix a bug without having to discard any inventories of potentially obsolete chips. Such chips might typically be in the ASIC manufacturing pipeline. In contrast, a new or partial mask set would have to be created with an ASIC or structured ASIC. If the new features or fixes obsolete the previous chip design, any chips in the manufacturing pipeline would have to be scrapped.
The higher development costs of chips that use the latest 90- and 65-nm process nodes may limit the number of design starts for several reasons. For starters, the total development cost of a moderate-complexity 90-nm design might be around $15 to $20 million. If the potential market is a million chips, the development cost only adds $15 to $20 per chip to the manufacturing cost. If the market potential is one-tenth that quantity, however, the amortized development cost hits $150 to $200 per chip. For designs at the 65-nm node, the development costs could be close to double those numbers. At such price points, an FPGA that sells for $200 to $400 might be just as cost effective as an ASIC.
The high cost of a high-complexity ASIC may discourage some designers from using a full-custom design and perhaps lead them to explore the structured-ASIC alternatives. Structured ASICs have lower overall development costs, as the silicon is pre-manufactured. Designers just have mask charges for the on-chip metal interconnect layers. Although NRE costs are lower, structured ASICs do have a higher per-chip cost than a full ASIC. Overall volume and performance will be the two main determining factors as to which path designers will take.
Another aspect that may have an effect on the number of ASIC design starts is the ability of designers to integrate more functionality on a chip as process features shrink. As integration levels rise, a previous-generation process’ two- or three-chip solution may end up being a single-chip solution in the latest process. Designers are bringing more memory onto chips to eliminate off-chip memory. To shorten design times, they’re using more blocks of licensed intellectual property. Rather than multiple design starts, only a single design start would therefore be initiated. Of course, new companies are always starting up. Each one may have its own ASIC needs. Yet many are turning to FPGAs for at least their initial proof-of-concept design--or even to get some beta systems into their potential customers’ hands.
Art captions:
Figure 1: ASIC design starts are projected to continue to decrease year over year through 2010. (Source: Gartner Group)
Figure 2: From 2004 to 2005, the percentage of ASIC design starts in each major world region has remained pretty consistent. Yet the overall number of design starts has decreased. (Source: Gartner Group)