An FPGA-Based Real Time Power System Simulator for Power Electronics
Corresponding author:
Julio C G Pimentel
Cisco Systems, Ottawa
3000 Innovation Drive
Kanata, Ontario, CANADA, K2K 3E8
Tel: (613) 2544599 Fax: (613) 2543333
E-mail:
Area of Interest: General-purpose, high-performance, PLD-based computing systems and applications
ABSTRACT
Introduction – This paper presents the work being done in the Power Electronics Laboratory of Laval University (LEEPCI) to develop a high performance digital real-time simulator for power electronics applications (DRTPSS) capable of simulating in real-time high frequency power electronic converters used in modern automotive and power conditioning systems.
The classical approach used to implement DRTPSSs consists in modeling the electrical network and devices in software (using a high level language such as C/C++) and using parallel processors and numerical integration techniques to solve the resulting equations. This is unfortunately subjected to the Read-Modify-Write processing model that imposes that the operations in each processor be realized sequentially. Also, the time spent to exchange information between the nodes of the parallel processor imposes a minimum time-step that can not be much decreased by using higher performance processors.
In this paper we present a completely new approach to implement DRTPSSs. Instead of using microprocessors or DSPs, we propose to use FPGAs as the main processing element and use a hardware description language (VHDL) as the modeling language. The network devices (RLC, diodes, IGBTs, etc.) are modeled in discrete time, described in VHDL and stored in a parameter-driven library. According to the network topology, the models are instantiated from the library, interconnected and mapped to an FPGA by automatic synthesis tools. Thus, the simulation runs directly in hardware so that it is neither subjected to the R-W-M paradigm nor to the inter-processor communication bottleneck which allow us to push the limits for the simulation time-step well below 30 us. Indeed, the initial results have shown that time steps of only a few microseconds are possible.
Summary - A general architecture of a DRTPSS consists in a library of device models and a representation of the power systems network (using the MNA or state-space methods) coded in a high-level programming language, and a high-performance digital computer that uses some sort of parallel processing topology [1][7][5][10]. A lot of research has been done in the last 20 years by the academic [][][][] and industrial [][][][][] communities aiming to decrease the minimum time-step of the DRTPSS. Programmable logic devices such as FPGAs (Field Programmable Gate Arrays) and CPLDs (Complex Programmable Logic Devices) are becoming more and more affordable and their performance continues to increase. They are used in many applications as an alternative to DSPs and high-performance processors. Present trends are towards hybrid solutions based on FPGAs and processors on the same board to optimize cost and performance [1] [4] [12]. Since CPLDs and FPGAs are programmable devices, the application can be implemented directly in hardware and the processing time can be reduced by exploiting the parallelism inherent to many algorithms.
Key elements and conclusion - As far as the authors know, FPGAs and PLDs have never been used before as the main simulation engine in DRTPSS. The main contribution of this work are: a fully integrated design methodology for DRTPSS centered on the use of FPGAs; increase of simulation stability by decreasing the decouple delay from two time steps to one time step; and implementation of better models for the nonlinear devices. The results presented show that the proposed simulator produces simulation results comparable to those obtained with the PSB from Mathworks. Besides, the initial results presented in this paper show that the technique has the potential to create a breakthrough in the DRTPSS and set a new level of performance for those simulation tools.