Activity 7.2A – J-K Flip-Flop Operations
Purpose
1. To construct J-K Flip Flop synchronous clock circuit and test its operation.
2. To develop Timing diagrams for a synchronous clock Flip Flop circuit
3. To construct J-K Flip Flop Asynchronous clock circuit and test its operation.
4. To develop Timing diagrams for an Asynchronous clock Flip Flop circuit.
Equipment
Computer Simulator
5 volt power Supply
IC chip: 7476
Breadboard and jumper wires
Logic Switches
Pulse Generator
LEDs and limiting resistors
Graph paper
Procedure
Part 1:
Background Information:
The J-K flip-flop (FF) is the most widely used type of flip-flop. It is called the universal flip-flop because of its versatility. Applications like counters, registers, data storage devices, frequency dividers, etc., use the J-K flip-flop.
Note: The designation J and K to name the inputs has no significance at all. The reason these letters were chosen is the fact that they are adjacent letters in the alphabet, and normally they are used to designate integer quantities in computer programming.
The operation of this flip-flop is almost identical to that of the S-R flip-flop. The J-K flip-flop behaves identically to the S-R flip-flop in the SET, RESET and the NO CHANGE conditions. The only difference is that the J-K flip-flop does not have an invalid state. In replacement of the INVALID state of the S-R flip-flop, the J-K flip-flop has a state called toggle. When the input conditions needed to achieve the toggle state is reached, the flip-flop output reverts to the previous state.
Operation
The general operation of a positive edge-triggered J-K flip-flop is summarized as follows:
· SET: When J is high and K is low, the flip-flop is in the set state. This means that Q is high and is low.
· RESET: When J is low and K is high, the flip-flop is in the reset state. This means that Q is low and is high.
· NO CHANGE: If both J and K are low, the output of the flip-flop remains in the same state as before the application of the inputs.
· TOGGLE: If both J and K are high, the output of the flip-flop will revert its state. If previous to the application of the inputs the output conditions were Q = and = , where is the level prior to the clock transition, then after the clock transition the state of the output will be Q = and = .
The logic diagram of an J-K flip-flop is shown below. On the left is the positive edge-triggered flip-flop, and on the right is the symbol that represents the logic symbol for the negative edge-triggered flip-flop. (Notice the bubble at the clock input.)
Logic Diagram of J-K Flip-Flops
The truth table of the positive edge-triggered flip-flop is shown next. The negative edge-triggered flip-flop has the same truth table but the output appears only at the falling edge of the clock pulse (ß).
Truth Table for the Positive-Edge-Triggered J-K Flip-Flop
The basic logic diagram for a positive edge-triggered J-K flip-flop is shown below. Notice that the difference between this flip-flop and the positive edge-triggered S-R flip-flop is that the outputs Q and are connected back to the inputs K and J respectively.
Logic Circuit for a Positive-Edge-Triggered J-K Flip-Flop
Example 1:
Shown is a negative-edge-triggered J-K flip-flop with input waveforms CLK, J and K applied to it. Determine the Q and output waveforms. Assume that the flip-flop is initially RESET.
Solution:
Asynchronous Inputs
Up to this point we have only looked at flip-flops with synchronous inputs. This means that the bits on these inputs are transferred to the outputs in synchronization with the clock (only on the triggering edge of the clock pulse).
In reality, most manufacturers of integrated circuit flip-flop include asynchronous inputs. These are inputs that, when active, act independently of the clock. They are normally labeled preset (PRE) or direct set (SD), and clear (CLR) or direct reset (RD). When the PRE is active the state of the flip-flop will always (as long as the preset is active) be SET; if, on the other hand, the CLR is active, the state of the flip-flop will be RESET.
In both cases the clock will not play any role in establishing the condition of the flip-flops. Asynchronous inputs override the effect of the synchronous inputs J, K and the clock (CLK). The active level of these asynchronous inputs may be active HIGH or active LOW.
The logic diagram of a positive-edge-triggered J-K flip-flop with active-LOW preset () and clear () asynchronous inputs (as is indicated by the bubble) is shown below. In order to activate these inputs you must apply a LOW.
Application of the Flip-Flop as a counter
Flip-Flops are commonly used in counter circuits. Because each flip-flop in a counter has to be clocked by an external clock pulse we can have two possible ways to clock them:
Asynchronous counters:
· These are counters where only the first flip-flop is clocked by an external clock. All subsequent flip-flops are clocked by the output of the preceding flip-flop. These types of counters are also called ripple counters because clock pulse ripples from one flip-flop to the next. Asynchronous counters are slower than synchronous counters because there is delay in the transmission of the pulses from flip-flop to flip-flop.
Synchronous counters:
· In synchronous counters the external clock is connected to all of the flip-flops so they all are clocked simultaneously.
Part 2:
1. For the circuit shown below, sketch the expected output waveforms for signals Q PET and Q NET.
2. Using the simulation software, construct the circuit of the Asynchronous counter shown.
Why is this circuit called Asynchronous?
Run the simulation with S1, S2, S3, R1, R2, R3 all set high as shown.
Using graph paper copy the waveform diagram that is produced. Include the Clock, L1, L2 and L3 in the graph. Tape the graph below.
How does the LENGTH of waveform L1 compare to L2 compare to L3?
Test the operation of the circuit and complete the chart below:
Breadboard this circuit.
Demonstrate the circuit operation to the teacher and get signature______
Based on your work with the circuit in #2, answer the following questions:
· What is an active low input?
· What is an active high input?
· How does the Set (Preset) affect the output of each chip?
· How does the Clear (Reset) affect the output of each chip?
· How can you tell if the Set (Preset) is active high or active low?
· What happens if both the Set (Preset) and Clear (Reset) are active?
· Define in your own words what an Asynchronous input is used for?
3. Using the simulation software, construct the circuit of the Synchronous counter shown. Place the switches in the positions shown in the diagram.
Run the simulation, and complete the waveform (Timing diagram).
Make the following switch changes to the original circuit. Run the simulation and observe the outputs and waveforms.
· Change Set1 to low. What happens to circuit operation?
· Change Set2 to low, return Set1 to high. What happens to circuit operation?
· Put both Set1 and Set 2 high. Change Reset1 to low. What happens to circuit operation?
· Change Reset2 to low, return Reset1 to high. What happens to circuit operation?
Conclusion
1. What is the difference between an Asynchronous and Synchronous Clock circuits?
2. Asynchronous clock and Synchronous clock circuits:
Using the knowledge gained from doing the Computer Simulation activities above, create, using the two flip flops contained in a 7476 IC chip, a circuit that will count continuously from 0 to 3. Connect the Preset, Reset, J-K inputs to obtain proper operation.
First: Wire an Asynchronous clocking circuit. When the circuit works correctly, demonstrate the circuit to your teacher, and get signature:
Teacher signature for Asynchronous clock circuit: ______
Second: Wire a Synchronous clocking circuit. When the circuit works correctly, demonstrate the circuit to your teacher, and get signature:
Teacher signature for Synchronous clock circuit:______
3. Design, simulate and build a ripple counter that counts from 0 to 15 (in binary of course).
Tape a copy of your simulated design below.
Demonstrate the circuit to your teacher and get signature:______