AC and DC modeling of the Vertical Diffused MOS Transistor

Yashar Pourali,1Reza Hosseini2, Neda Teimourzadeh2*

1Department of Electrical Engineering, Tabriz Science and Research Branch,Islamic Azad University, Tabriz, Iran

2Department of Electrical Engineering, Khoy Branch, Islamic Azad University, Khoy, Iran

Corresponding author:

Abstract: In this paper, we present the simulation results of an equivalent circuit model for a vertical diffused MOS (VDMOS) transistor. Separate parts of the transistor are modeled using common electrical elements. Ac and DC behaviors of the proposed model are investigated separately. The DC characteristics are investigated by applying different DC voltages in the input. Also, the AC characteristics are simulated by applying an AC voltage source (10KHz-10GHz) in the input. As a result, IV curves, transconductance and frequency response of the device are derived. It is shown that the proposed circuit model can operate in frequencies up to 2.5 GHz.

  1. Introduction

Versatileusage of wireless communications has created a demand for low cost, linear, high-gain RF power transistors that can be operate able in base station power amplifiers.Power MOSFETs are widely used as switches in power systems. Therefore, MOSFETs are required not only to have a high breakdown voltage , but also a low on-resistance, as well as a body diode with superior reverse recovery characteristics to suppress radio noise and voltage surges[1-5].It has been recently demonstrated that some anomalous failure phenomena observed in last generation high current-low voltage VDMOS devices characterized by a short channel length operating at low drain current are due to an unexpected thermal instability similar to the effect commonly observed in BJT’s. For the advantages of the high input resistance, the low driving power, the superior frequency characteristic and the low noise, the VDMOS has been widely used in the motor speed regulation, the Hi-Fi audio, the automotive electronics and so on[3].

In this paper, We model the separate parts of the VD MOSFET using common electrical elements and analyze the DC and AC behaviors of proposed Model.In the AC section, the three important capacitances, Cgd ,Cgs and Cds, have been modeled. Finally, the comprehensive model is verified by the comparisons with the measured Ids_Vds curves, the Ids_Vgs curves and the capacitance curves, which show the good accuracy.

  1. Circuit Model

To model the electrical behavior of the VDMOS transistor we should first take a look at its inner parts.An appropriate combination of physical models which represent the device physics should be used to model the intrinsic behavior of the device. A typical VDMOS transistor is depicted in Fig. 1.

Figure 1: A typical VDMOS transistor [5]

As we can see in Fig.1, the most evident difference of a VDMOS from a conventional MOS is its vertical structure. This vertical structure can be understoodby noticing the position of the drain.

VDMOS transistor, also, differs from Conventional MOSFETs in some of the fabrication steps. For example it has a higher quality gate oxide because it is being formed in the first steps of the fabrication process.The quality of the gate oxide is very important in a transistor because of good control of the threshold voltage. Also in power applications, a high quality gate oxide leads to higher voltages.Detailed fabrication steps of a VDMOS transistor can be found in the literatures [6-10].

Different electrical behaviors of the VDMOS transistor can be modeled using equivalent electrical elements. The first of all can be its resistive behavior. Fig.2 shows internal resistors that can be considered for a VDMOS transistor.

Figure 2: Internal resistors of a VDMOS transistor.

Different parts of the transistor show resistance as the transistor turns on. These resistances are as follows: resistance of the inverted channel (Rch), resistance of the accumulated region (RA), resistance between the body and the drain (RDO = RJ + RD) and the resistance of the substrate (Rsub). So, the VD MOS on_stateresistance can be defined with equation1.

(1) / RDS(on)=Rch+RA+RDO+Rsub

Another important behavior is the capacitive behavior of the on state. This behavior is shown in Fig. 3. Cgd, Cgs and Cds model the capacitive behaviors which exist between gate-drain, gate-source and drain-source sections of the transistor, respectively.

Figure 3: capacitive behavior of the VDMOS transistor.

To consider the parasitic inductive behavior of the transistor, it can be included inductances in the input and output nodes of the transistor.

To calculate the values of resistors, capacitors or inductors which are used in proposed model, one should know the exact physical behavior of the different parts of the transistor. There are stable formulas for these calculations that can be found in the literature [8-10].

The most important part of the VDMOS transistor may be its channel that creates the current. To model the channel and also the current production behavior, we have considered an NMOS transistor. Also there is a parasitic JFET that can be considered in the model.

The comprehensive proposed circuit model of the VDMOS transistor is depicted in Fig. 4.

As it can be seen in Fig. 4, input and output sections of the model consist of parasitic capacitors, inductances and resistors. There also exists a body diode that occurs between drain and the body.

We have considered AC and DC voltage sources (Vin-AC and V-in DC respectively) in the input to study the DC and AC behaviors of the proposed model.

There also exists a DC voltage source in the drain node (VD) which is used to biasing purposes.Electrical elements which are used in the model of Fig. 4, are listed in table 1 .

Figure 4: proposed circuit model for the VDMOS transistor.

Table 1: List of electrical elements that are used in the model of Fig. 4.

Description / Electrical element
Drain-gate capacitor / Cgd
Parasitic input capacitance / Cin
Parasitic capacitor of gate / Cg
Parasitic capacitor of gate-source / Cgs
Parasitic capacitor of drain / Cd
Parasitic capacitor of load / Cout
Parasitic input inductance / Lin
Parasitic inductance of gate / Lg
Parasitic inductance of source / Ls
Parasitic inductance of drain / Ld
resistance of the load / Rout
Gate resistance / Rg
Source resistance / Rs
Drain resistance / Rd
nMos to model the channel / M
Parasitic JFET / J
Body diode / D
Drain bias voltage / VD
Input AC voltage / Vin-AC
Input DC voltage / Vin-DC
  1. Simulation results
  1. DC analysis

To analyze the DC behavior of the proposed model, we have simulated the model of Fig. 4 using ORCAD software package with a DC bias at the input (Vin-DC). The DC input voltage is changedfrom 2 to 10 volts with steps of 2 volt. We also have changed the drain voltage (VD) from 0 to 40 volts. Plots of ID versus VD with different VGs as input are shown in Fig. 5. As it is obvious in Fig. 5, the output current increases with increasing voltage and in some point, it gradually saturates.
Figure 5: ID vs VD for different DC input voltages at the input (VG).The input voltage is changed from 2 to 10 volt with steps of 2 volt. We have also calculated in Fig. 6.

Our studies demonstrate that the proposed model provides results which agree well with measured results. An example is given in Fig.6.

Figure 6: Calculated gm values vs VD. 4 plotted curves differ in the DC voltage at the gate that is changed from 2 to 8.

To further investigate the model, we have changed the gate voltage in the ranges of 3 to 4 volts and 6 to 8 volts. Results are shown in figures 7-10.

Figure 7: ID vs VD for different DC input voltages at the input (VG).The input voltage is changed from 3 to 4 volt with steps of 0.2V.
Figure 8: Calculated gm values vs VD. 5 plotted curves differ in the DC voltage at the gate that is changed from 3 to 4.
Figure 9: ID vs VD for different DC input voltages at the input (VG).The input voltage is changed from 6 to 8 volt with steps of 0.5 volt.
Figure 10: Calculated gm values vs VD. 4 plotted curves differ in the DC voltage at the gate that is changed from 6 to 8.
  1. AC analysis

To analyze the AC behavior, we have applied the input with an AC signal (Vin-AC). We have swept the input frequency in the range of 10KHz to 10GHz. The result is plotted in Fig. 11.

As we can see in this figure, the frequency response of the proposed model (considering the cut off frequency as 10% of the peak value), falls at the frequency of approximately 2.5GHz. So we can conclude that the proposed model is capable of operating at the RF frequencies. Therefore the proposed model can be used in high power RF applications to facilitate the circuit designing scheme.

Figure 11: Frequency response of the proposed circuit model of Fig. 4. The AC input is swept in the range of 10KHz-10GHz.
  1. Conclusion

A circuit model is proposed for the VDMOS transistor that can operate at frequencies as high as 2.5 GHz. Since the proposed model consists of resistors, inductors and capacitors, it is capable of being used in both DC and AC analyses.

DC and AC simulations are done using ORCAD software package. As a result, Id curves vsVd are extracted. Also we have calculated gm values for different DC voltages applied to the gate. Frequency response of the transistor is calculated for AC input voltages in the range of10KHz to 10GHz. It is shown that the cut off frequency of the proposed model is 2.5GHz. We have compared our simulation results with the theoretical and experimental results from the literature. We have shown that the proposed model have output characteristics that are in a good agreement with these results.

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