Project 15
MOSFET Amplifiers with Current Source Biasing
Objective: This project will focus on the use of FET current mirrors to provide the DC biasing for Common Source and Common Drain amplifiers, two of the primary FET amplifier stages. The design of each amplifier type (CS and CD) to achieve a specific design goal using current biasing will be examined. The frequency response and feedback adjustments will also be investigated.
Components: 2N7000 FET
Introduction:
One of the primary differences between discrete and integrated amplifier design, as mentioned in Project 11, is the use of biasing resistors. The savings in "semiconductor real estate" is even more dramatic when the resistor area is compared to that of the active FETs. The ability to easily change the W/L ratios for the FETs used in the current source (see project 13 for additional discussion) provides great flexibility in selecting the size of the required power supply(ies) as well as in the value of the load currents. As in most semiconductor device fabrication, "exact" parameter values are difficult and expensive to obtain while matched device parameters are basically a "side effect" of the overall process. This "side effect" makes FET based current sources well suited for integrated circuits since the FETs are used for the entire source. This project will examine the use of an FET current mirror, as discussed in Project 13, to provide the DC bias for a Common Source and a Common Drain amplifier. The actual AC amplifier analysis and design is the same for both discrete and integrated circuits once the related changes due to the new biasing network have been incorporated. The students are referred to Projects 9 and 10 for detailed discussions on the AC analysis of the single transistor amplifier types. A discussion of the changes associated with current biasing will be the focus of this project.
Figure 15-1 shows the Common Source Amplifier with the biasing current source in the source branch. The drain current is equal to the bias current since there is no gate current for the FET and it is therefore independent of the transistor device related parameters such as VT and K. This independence removes the need to try and provide a stable bias circuit using gate resistors in conjunction with a source resistor. The designer is then allowed to adjust RG to improve the input impedance without having to worry about the relationship between RS and the gate bias network or the dissipation power associated with very large gate resistors.
The small signal gain for this circuit is:
which shows how RG can be adjusted to improve the coupling of the source signal into the amplifier and thus increase the overall voltage gain. Note that in the gain equation is the effective source resistance of . Feedback can still be provided by placing a resistor (RS) in series with the current source by-pass capacitor (CS).
A Common Drain amplifier with current source biasing is shown in Figure 15-2. The biasing current is again included in the source branch. The drain current and RG can be adjusted effectively independent of the specific transistor parameters in order to meet design input, output, and gain specifications. Notice that RS has also been eliminated from the circuit through the use of current biasing. Again, as in the Common Source amplifier, the voltage gain for the Common Drain amplifier is a strong function of the value chosen for RG. As seen from the small signal gain equation:
the voltage gain approaches the theoretical limit of 1 for a large range of loads when . The current source impedance and the transistor output impedance are represented by rds1 and rds2 respectively in the above equation and represents the effective source resistance of .
Figure 15 - 1: Common Source Amplifier with Current Source Biasing
Figure 15 - 2: Common Drain Amplifier with Current Source Biasing
Design:
1. Design a Common Source amplifier as shown in Figure 15-1 with the following specifications:
A. use a 2N7000 MOSFET and a 20 volt DC supply
B. midband gain VO/VS 6.0
C. low cutoff frequency FL between 100 Hz and 200 Hz
D. input impedance as seen by the source 20 k
E. VO symmetric swing 3.0 volts peak (6 V p - p)
F. load resistor RL = 5 k
G. source resistance RI = 50 (this is in addition to the function generator's
internal resistance)
H. FET current mirror to meet bias current specifications. You may assume you have a ± 20 V supply available.
2. Determine the value of RS to place in series with the CS shown in Figure 15-1 in order to provide feedback for the CS amplifier designed in step 1. The new voltage gain should
be 2 while all other specifications remain unchanged.
3. Design a Common Drain amplifier as shown in Figure 15-2 with the following specifications:
A. use a 2N7000 MOSFET and a 20 volt DC supply
B. midband gain VO/VS 0.7
C. low cutoff frequency FL between 100 Hz and 200 Hz
D. input impedance as seen by the source 10 k
E. VO symmetric swing 5.0 volts peak (10 V p-p)
F. load resistor RL = 200
G. source resistance RI = 50 (this is in addition to the function generator's
internal resistance)
H. FET current mirror to meet bias current specifications. You may assume you have a ± 20 V supply available.
Pre-Lab Procedure for Lab 16: (This information is needed for the required JFET amplifier design)
1. Find the value of the threshold voltage VP and IDDS from the digital curve tracer.
2. Determine the value of ro from the digital curve tracer. The slope of the transistor
ID-VDS curves in the active region is 1/ro.
Lab Procedure: (steps 1 & 2 may be omitted if done prior to this lab period and the same FET is used)
Note:
The MOSFET can be easily damaged by static electricity, so careful handling is important
1. Find the value of the threshold voltage VT and conductivity parameter K from the digital curve tracer (remember the relation ID = K[VGS - VT]2 in the saturation region).
2. Determine the value of rds from the digital curve tracer. The slope of the transistor
ID-VDS curves in the active region is 1/rds.
3. Construct the CS circuit shown in Figure 15-1. Remember, RI is installed in addition to the internal 50 resistance of the function generator.
4. Verify that the specifications have been met by measuring the Q-point, midband voltage gain, and peak symmetric output voltage swing. Note any distortion in the output signal.
5. Adjust the output signal to obtain the maximum, non-distorted output voltage swing. Is the design specification met?
6. Observe the loading affect by replacing RL first by 500 and then by 25 k. Note any changes in the output signal and comment on the loading affect.
7. Use computer control to record and plot the frequency response. Find the corner frequencies and bandwidth to verify that the specifications have been met.
8. Measure the input impedance seen by the source [look at the current through RI and the node voltage on the transistor side of RI] and the output impedance seen by the load resistor [look at the open circuit voltage and the current through and voltage
across RL]. Verify that the input impedance specification has been met.
9. Now insert the RS determined in step 2 of the design section in series with the by-pass capacitor CS to form a series-series feedback configuration. Measure the Q-point and midband voltage gain. Note any distortion in the output signal.
9. Repeat steps 4 - 8.
10. Construct the CD circuit shown in Figure 15-2. Remember RI is installed in addition to the internal 50 resistance of the function generator.
11. Repeat steps 4, 5, 7, 8.
12. Observe the loading affect by replacing RL first by 50 and then by 750 . Note any changes in the output signal and comment on the loading affect.
Questions:
1. Could these circuits be supplied with a current source without using both positive and negative DC sources? Explain your answer.
2. Compare the gain, frequency response, input impedance, and output impedance of the CS amplifier with the results from the CE amplifier (Project 9 or Project 11). Compare the CD amplifier with the CC amplifier (Project 10 or Project 11). Comment on the differences/similarities.
3. Why is the current source bypassed for the CS amplifier but not for the CD circuit?
4. What value of load resistance results in maximum voltage gain? What load resistance results in maximum power transfer to the load? Answer these question for each amplifier type.
5. Compare the Lab measurements for each amplifier to the theoretical predictions (such as those obtained using PSPICE®). Note how increasing the feedback in the CS amplifier affects the gain, bandwidth, and input and output impedances.
6. Describe one or two methods that can be used to determine the effective impedance of the current source.
7. What, if any, limitations exist on the values used for RG and the operation of the current mirror load branch FET in terms of operating region(s) and load voltages?