EE 134 Digital Integrated Circuit Layout and Design
Winter 2006
Instructor: Prof. Roger Lake, x2122, , http://www.ee.ucr.edu/~rlake
Office hours: 4-5pm MW ENGR2 437
TA: Faruk Yilmaz,
Office hours: TBD
Lecture: TR 9:40-11am ENGR2 142
Labs: M 2:10-5pm and F 11:10-2pm ENGR2 128
Objective: The objective of this course is to introduce the student to CMOS digital integrated circuit layout and design. This course covers CMOS integrated circuit design, layout and verification using the CADENCE CAD tools. Topics covered are digital models, inverters, static logic gates, transmission-gates, flip-flops, and dynamic logic gates.
Text: “Digital Integrated Circuits,” (2nd ed.) J. Rabaey, A. Chandrakasan, and B. Nikolic, Prentice Hall, 2003. ISBN: 0-13-597444-5.
Online references:
http://www.ee.ucr.edu/~rlake/EE134.html
Laboratory: We will meet each week for the first 4 weeks to practice using the CAD software performing small layout and simulation assignments. From the 6th week on, the lab time will be used for the design project.
Exams: Midterm
Grades: 10% assignments, 20% lab, 50% design project, 20% midterm
Lecture material and announcements:
Students are responsible for all lecture material and announcements.
Course Contents
Week 1: Chs. 1&2. Introduction.
Week 2: Ch. 2. CMOS manufacturing, design rules, and packaging.
Week 3. Ch. 3. Basic MOSFET operation. Deep sub-micron MOS. Dynamic behavior.
Week 4. Ch. 5. Inverter. Voltage transfer curve. Capacitance. Switching delay time.
Week 5. Ch. 5. Sizing a chain of inverters.
Week 6. Ch. 5. Power and Energy
Week 7. Ch. 6. Complementary static CMOS gates
Week 8. Ch. 7. Static latches and registers
Week 9. Ch. 7. Static latches and registers
Week 10. Ch. 6. Dynamic logic gates