ABHIJEET JOGLEKAR

50 S. Central Campus Drive, Phone: (801) 363-6078 (H)

Room # 3190, (801) 581-3012 (W)

School of Computing, Email:

Salt Lake City, Utah-84112 Web:

OBJECTIVE

To obtain a full-time position in software design and development.

AREAS OF INTEREST

Computer Networks, Operating Systems, Distributed Systems, Embedded Systems.

EDUCATION

Aug’ 00-Present M.S. Computer Science (Expected Graduation Date: Oct’03)

University of Utah

GPA: 3.9 / 4.00

Aug’94-May’99B.E. Computer Science

M.Sc Mathematics

Birla Institute of Technology & Science, India

GPA: 8.43/10.00

WORK EXPERIENCE

Jul’99-Jul’00 Software Engineer, Motorola India Electronics Ltd., India
  • Worked as part of a three-member team to port the H.323 stack (ITU-T standard for Multimedia over packet based networks) from a Windows PC platform to an embedded device consisting of a MPC823 board interfaced to a DSP56300 core. My contribution was:
  • Porting the application’s network module from Winsock API to Unix sockets API.
  • Developing the host side driver for Hi08 host interface to the DSP.
  • Designing an audio API layer between the application and the driver.
  • Changing the application’s audio module to use the new API instead of directly calling Windows functions.

Development environment was C, Microsoft Developer Studio, Windows and Solaris based cross-compilation and debugging tools for MPC823 board.

  • Developed an audio streaming server based on Real-time Streaming Protocol (RTSP) and Real-time Transport Protocol (RTP) on a Windows PC platform. Development environment was C and Microsoft Developer Studio.
Jan’99-Jun’99 Internship, Motorola India Electronics Ltd., India
  • Worked as part of a two-member team to develop a videoconferencing gateway between an H.323 and H.324 stack (ITU-T standard for Multimedia over telephone networks) on a Windows PC platform.
  • Studied the call signaling and control signaling protocols, real-time data transfer protocols and media algorithms used in the two standards. (H.245, RTP, RTCP, G.723, G721, Q.931)
  • Designed the conversion module at different layers between the protocols.
  • Implemented the gateway and demonstrated a multimedia call between an H.323 and H.324 endpoint through the gateway.

Development environment was C and Microsoft Developer Studio.

SKILL SET

Operating Systems: Unix (FreeBSD, Linux, Solaris), Windows (NT, 9x), pSOS, VxWorks

Languages: C, C++, Intel x86/ Motorola assembly

Embedded Platforms:Intel IXP1200 network processor, Motorola MPC823/MPC821

Technologies:TCP/IP stack protocols, distributed systems, PC based and embedded multimedia communication devices, network emulation

Standards:H.323, H.324, RTP, RTSP, Q.931, H.245, G.721, G.723

Tools:Clearcase, CVS

RESEARCH EXPERIENCE

May’01-Present: Research Assistant, Flux Group, Univ. of Utah (

Research Project: Netbed/Emulab Network Testbed (

MS Thesis Title: “High Capacity Network Link Emulation using Network Processors.”

Advisor: Prof. Jay Lepreau ( )

(In progress)

Network link emulation is an important part of network emulation, wherein links in the topology are emulated to subject the end-user traffic to different bandwidths, latencies, packet loss distributions, and queuing algorithms. Existing solutions use general-purpose PC’s for quick implementation and easy deployment. However, a PC architecture does not typically scale to large packet rates, thereby limiting the size of the emulated topology. In this thesis, we explore the use of network processors as a high-capacity platform for link emulation. The IXP series of network processors from Intel uses multiple independent programmable microengines, each supporting hardware multithreading and low overhead context switches on memory and IO references. This highly parallel and optimized architecture can support large packet rates while leaving enough headroom for application specific processing. We validate our claim by designing and implementing a link emulator on the IXP1200 network processor.

Aug’98-Dec’98: Bachelors Thesis, Birla Institute of Technology & Science, India

Thesis Title: “Performance Evaluation of a Two-Level Rollback Recovery Scheme.”

Advisor: Prof. JP Mishra

We evaluated the performance of a two-level rollback recovery scheme using the probability of task completion on a system with limited repairs as the metric.

PUBLICATIONS

  • An Integrated Experimental Environment for Distributed Systems and Networks.

Brian White, Jay Lepreau, Leigh Stoller, Shashi Guruprasad, Mac Newbold, Mike Hibler, Chad Barb, Abhijeet Joglekar (In the Fifth Symposium of Operating Systems Design and Implementation, Dec. 2002)

(

  • A Scalable, Accurate and Extensible Network Emulation Platform using the IXP1200 Network Processor.

Abhijeet Joglekar (Submitted to the Intel IXA University Program, Student Design Competition)

(

  • Performance Evaluation of a Two-Level Rollback Recovery Scheme.

Abhijeet Joglekar (Thesis. BITS, Pilani, India. Dec. 1998)

TEACHING EXPERIENCE

Aug’02-Dec’02:Data Communications and Networking

Jan’01-May’01:Data Structures and Algorithms

Aug’00-Dec’00:Data Communications and Networking

MSCOURSE WORK

Advanced Networking, Advanced Compilers, Advanced Computer Architecture, Foundations of Computer Science, Compilers, Programming Languages and Semantics, Computer Systems Seminar.

COURSE PROJECTS

  • Stack Walker on X86/Sparc architectures.
  • User-level threads library on Unix.
  • Link-time garbage collector.
  • Compiler for a simple Java-like object oriented language.
  • Simulation and Performance Evaluation of On-Demand Multicast Routing Protocol (ODMRP) on ns-2.

GNUtella like peer-to-peer network.

  • Simple web client and web server.

REFERENCES

  • Prof. Jay Lepreau, School of Computing, University of Utah ()
  • Prof. John Carter, School of Computing, University of Utah ()
  • Suresh Anupindi, Project Manager, Motorola India Electronics Ltd. ()

VISA STATUS

F-1.

Abhijeet Joglekar