3.5.2 Front End Electronics

3.5.2 Front end electronics

3.5.2.1 General considerations

According to the physics design, The BESIII detector will mainly be composed of five subdetectors which are Central Trigger chamber (CT), Main Drift Chamber(MDC), Time-Of-Flight plus Cherenkov Correlated Timing counter (TOF+CCT), Electromagnetic Calorimeter(EMC, Barrel and End), Muon Counter(MC, Barrel and End). All information of the physics processes that the experiment studies are carried in the output signals of these subdetectors. The purpose of each subdetector is different so is the design requiremen, and they are relatively independent to others. Correspondingly, the BESIII electronics will also be in five subsystems with the common functions of signal amplification and formation, amplitude and time information extraction, digitization, and subevent packing. The subevent data will be merged together to form the event data which then be transferred to on-line farm via switch network for further processing. Finally the data will be recorded on tapes for offline physics analysis. The main technical specifications for each electronics subsystem are listed in the table 3.5.2.1-1.

Table 3.5.2.1-1 Required specifications for BESIII electronics

Item / number
of
Channels / time measurements / Charge measurements / Count rate/ per channel / Infor- mation to
trigger
range / number
Of ch. / σt / Range / number
Of ch. / σQ
CT / 300 / 0.22fc on
average / 300 / 20% at
0.22fc / 20k / hit
MDC / 6000 / 500ns / 6000 / 0.5ns / 10 fc –
1500fc / 6000 / 4 fc / 100k / hit
TOF
+CCT / 160(TOF)
160(CCT) / 60ns / 320×2
(double
threshold) / 25ps / 2Vmax
for TOF,
0.2Vmax
for CCT / 320 / 2%at 2v
forTOF, at o.2v
for CCT / hit over
high vth of TOF
EMC
(Br.) / 22000 / 4 fc –
300 fc / 22000 / 0.2 fc / 1k / sum of
analog
EMC
(End) / 800 / 60ns / 800 / 25ps / 0.2vmax / 800 / 0.5%
at 0.2v / 1k / sum of
analog
Muon
(Br.) / 20000※ / hit measurements / hit
Muon
(End) / 20000※ / hit measurements / hit
Total electronics channel / 76,860

Note: the figures marked with sign “※” in above table are estimated value.

As shown in table 3.5.2.1-1, the main tasks for BESIII electronics can be summarized as following:

①To measure the time information carried by detector signal, with a time resolution 0.5ns for MDC, 25ps for <TOF+CCT > and End EMC.

②To measure the charge carried by detector signals( the signal’s amplitude).

③To extract the trajectory position(x, y) information in detector.

④To provide the hit information and the sum of analog signals for trigger system.

The total number of electronics channels is about 77K which is 3 times more than that of BESII electronics.

Compared with BESII, the BESIII electronics confronts with many technical challenges. The main reasons are:

①BEPCII machine will run with multi-bunch in the storage ring with a bunch spacing of 8ns. The electronics system must adopt a very new design strategy to acquire the information from detector signals.

②The luminosity of BEPCII will reach 1×1033cm-2s-1 which is 2 order of magnitude higher than BEPCI. This means the data amount to be acquired and processed by BESIII electronics, is greatly larger than BESII, the speed for data processing must be much faster.

③The e- and e+ beam intensity of BEPCII will each reach 1100ma, which is 40-50 times that of BEPCI, and the beam lifetime is only half of that of BEPCI, so the background signals in BESIII electronics will be much more than that in BESII . The signal rate for inner detector, especially for the MDC will be much higher.

Considering the above factors, the design of BESIII electronics will take the following technical strategies:

①The pipeline technique will be used to make sure any interesting event will not be lost during trigger decision.

②Multi-stage parallel processing technique will be adopted to make the system dead time very small.

③The front-end cards/digitization modules will be located as close as possible to the detector to shorten the length of analog cables. The digitized data will be transferred to the counting room via a few optical fibers.

④Much effective technical measures must be taken to make the system to be immune from any possible RF interference.

⑤The modules with the same functionality in different subsystems will take same design specifications to make these modules interchangable among the subsystems. By this way, the cost can be dropped down, and the future maintenance will be easy.

⑥The VMEbus, widely used by the HEP experiments in the world, will be adopted as the system bus standard. The PowerPC will be used as the communication interface with online farm.

Based on the considerations mentioned above, a simplified block diagram of BESIII electronics system is shown in Fig. 3.5.2.1-1.

3.5.2.2 Main Drift chamber electronics

The main tasks for the MDC electronics are:

①To measure the drift time of ionized electrons towards the sense wires, so that determine the spatial trajectory of particles flying through the chamber. The main design specifications are as follows:

Time range to be measured: 0-500ns

Time resolution σt: ≤0.5ns (the timing error is not taken into account here).

②To measure the charge deposition on a sense wire, so that calculate the particle’s energy loss dE/dX in the chamber. The following specifications are required for the charge measurement:

Charge range to be measured: 10-1500 fc

Charge resolution σQ: 4 fc

③To provide the sense wire hit information to the trigger system.

With consideration of above requirements, the MDC electronics is designed to consists of 6 sections which are the preamplifier, main amplifier, charge measurement circuitry, time measurement circuitry, calibration and logic control circuitry. The system block diagram is shown in Fig. 3.5.2.2-1.

⑴ Preamplifier

As it is well known, the particle’s energy losses in the chamber obey the landau distribution. The signal size in the low energy end of the distribution is very small, so the signals from sense wires must be amplified properly to make them suitable for further processing by subsequent circuitry. The following points in designing the preamplifier will be taken:

①A transimpedance type preamplifier will be designed, to preserve the time information carried by the signal’s rising edge.

②To reduce the noise level, the input impedance of preamplifier, which matches the characteristic impedance of sense wire, will be designed with so called “cold termination” technique. The preamplifier card will be directly mounted on the endplate of chamber.

③The power dissipation should be controlled no more than 50mw/per channel, so that no any auxiliary cooling measures is needed.

④The preamplifier will be designed and fabricated as a hybrid IC chip. Each chip consists 4 or 6 channels depending on the arrangement of chamber feedthrough.

The signal wire layers of MDC, especially inner signal wire layers, are very close to the collision point. Therefore it is very important to design the preamplifier with low noise methodology.

⑵Main amplifier

The main task and basic design requirements for main amplifier are:

①To split the signal from preamplifier into two branches, one for charge measurement, another for time measurement.

②The signal in charge branch feeds to a RC filter and shaper to smooth the waveform suitable for the FADC sampling. According to a rough estimation, the hit rate of inner signal wire will be as high as 100k/s. To avoid the signal pile up, the shaping width will be controlled not more than 600ns. In this case, the probability for signal pile up can basically be negligible.

③The signal in time branch is sent to a fast discriminator with a low threshold voltage to deliver a timing pulse, whose leading edge corresponds to the drift time. The timing error caused by time walk will be corrected using corresponding charge value in offline processing.

④If some cells in the chamber are fired, a hit signal will be produced and sent to trigger system for trigger processing.

Fig. 3.5.2.2-2 is a simplified block diagram of the main amplifier.

The main amplifier can be designed as a VME module. 32 channels per module should be possible.

⑶Charge measurement

As mentioned above, the hit rate for inner layer wires is very high(100k/s), hence the charge measurement will take the digital pipeline scheme based on Flash ADC(FADC). The charge value carried by wire signal can then simply be extracted by numerical integration. According to the requirement for measurement precision, a FADC with 10 bit resolution and 40 MHz sampling rate will be used. The sampling clock will be synchronized with the collision bunch.

The Fig. 3.5.2.2-3 shows the simplified block diagram for charge measurement. In the diagram, the analog processing circuitry receives the dE/dX signal from main amplifier, then some necessary processing such as gain adjustment, DC level shift, signal driving and the high frequency noise filtering will be performed here to make the signal match the input characteristic of FADC chip. The FADC digitizes the signal with 40MHz rate, the digitized data will be written into a digital pipeline with the same clock. The pipeline is made of a circular dual port memory (DPM). The length of DPM should be greater than the trigger latency. With the trigger latency equal to 2.4us, an 8bit depth DPM would be enough. A clock counter provides the write address for the DPM.

The read clock for DPM is the same as the write. A subtracter (a block marked with “-“ in the diagram) provides the read address for the DPM. Normally the read clock input of the DPM is open, therefore the data in the DPM will not be readout in spite of where the read pointer points to. In this case, the old data in the cells of DPM will be overwritten by new one circularly.

The subtracter has two inputs, one receives the output of clock counter, another is connected to a constant value “trigger latency”. The output of the subtracter, i.e., the difference between the output of clock counter and trigger latency will be used as the read address for the DPM.

When the trigger L-1 is active, its leading edge will immediately start the following procedures:

①To ask the subtracter to subtract the trigger latency from the current output of the clock counter, the difference value is used as the read address for the DPM. It is obviously that the read address at this moment is just the write address when an interesting event was produced at the moment t = t. The digitized data related to this event in a channel must be stored in the cells starting from the current read address. The number M of these cells possibly occupied by these data should be “maximum drift time + signal width”.

②To ask the processing logic circuitry to close the switch (sw) immediately, the read clock will be active from this moment. The data starting from the t = t then will be readout from DPM to the buffer1 one by one. After reading for M times, all data related to the current event in this channel will have been transferred from DPM to buffer1.

③To make the trigger no. counter to increase its output value with 1. The resultant output will be the current trigger number. This trigger number should be readable out by VME. Also this counter should be resetable by VME and other external source, say the trigger circuitry.

④With a proper delay, to save the current content of the trigger no. counter into a trigger no. register.

After receiving a trigger number, the trigger no. register will set a flag bit ID to be equal to “1” immediately. Normally the processing logic circuitry always checks the ID bit. Once ID=”1” is found, the processing logic will read out a batch of data correspond to the current trigger number from the Buffer1, and then make a numerical integration over them to get the charge value, and finally compare this value with a threshold stored in a RAM. If the charge value is greater than the threshold, the processing logic will assemble the charge value with the trigger number, and then put it into the buffer2, waiting being read out by VME.

In each module, there is a global buffer(G_buf), which is used to keep so called “hit map” words. The length of each hit map word is 32 bits, and each bit represents a channel in the module. If the charge value in a channel is greater than threshold, the corresponding bit in the hit map word will be set to “1”, otherwise to “0”. When VME starts a read cycle, it will first read the hit map, from which the VME will know which channel has meaningful content and should be read out.

It can be seen from above description that the FADC conversion, data transfer from pipeline to buffer1, charge extraction, zero suppression and VME readout, all these five processes can be performed concurrently.

In the Fig. 3.5.2.2-3, all the logic functions in the upper dotted line block will be implemented by a part of FPGA (Field Programmable Gate Array). One FPGA will be enough for four channels, so in each module there will be 8 such FPGAs. All logic functions in the lower dotted line block will be performed by another so called global FPGA.

The module will be designed on 9U VME standard board(280mm×366.7mm or 220mm×366.7mm). 32 channels in one module is possible. Totally there will be 188 FADC module, and 11 of 9U VME crates will be needed.

⑷Time measurement

The time measurement module receives the discriminated signal from main amplifier. Its main task is to measure the time interval between the time t at which a good event was produced, and the leading edge of the discriminated signal. The time t is given by trigger system.

There are a number of optional schemes to perform time measurement. At present two schemes are considered as given below.

①Time measurement based on CERN HPTDC

As a first option, the HPTDC chip, which is designed recently with 0.25um CMOS technology by CERN microelectronics group, will be chosen as a key component for time measurement. This is a general time measurement chip with high performance aimed for time measurements for several large detectors at LHC which are being constructed. The first prototype chips are under testing in CERN at present. Its main specifications are as follows:

□No dead time.

□High integration. 32 channels on each chip.

□Good time resolutions with four programmable options(estimated):

～250ps RMS low resolution mode

～ 70ps RMS medium resolution mode

～ 35ps RMS high resolution mode

～ 15ps RMS very high resolution mode (8 channels)

□double pulse resolution: ～5ns.

□Cheap. ～RMB 600.0Yuan per chip.

Using the CERN HPTDC chips to design the MDC TDC module on a 6U VME standard board, it is expected that at least 64 channels per module is possible. For total 6000 time channels, the time measurement system can be setup with 94 6U- VME modules in 6 6U-VME crates.

②Time measurement based on <TAC + FADC>

The Fig. 3.5.2.2-4 shows a concept diagram for this scheme.

In the diagram, td is the drift time to be measured. The trigger clock is a pipeline clock according to which the trigger system makes trigger decision step by step. One trigger clock period (40ns) will cover 5 collision bunches (8ns).

Suppose at a moment t = t, an interesting collision occurred. At the moment t = td, the hit signal (discriminated wire signal) comes. As shown in the diagram, the interval td between the two moments is the time to be measured. It is obviously that the interval td contains two portions: a number of clock period, and a fraction of a clock called as mantissa tm. We have:

td = n×T + tm (a)

where n is an integer, i.e., the clock number the td covers. T(40ns) is the clock period. The integer n can be simply measured by countingthe clock number covered by the drift time. Therefore if tm can be measured, it will beeasy to get the drift time td.

It is rather complicated to measure the tm directly. But it can be seen from the diagram:

tm = T - tx

Therefore:

td = (n + 1) ×T – tx (b)

So the time measurement for tm can be replaced by measuring tx. An analysis proves that such replacement will greatly simplify the circuit design, and also the measurement precision will be better.

With the above considerations, the drift time measurement can be divided into two parts: one counts the clock number (integer) covered by drift time, another uses <TAC + FADC> scheme to measure the tx precisely. Thus from equation (b), the drift time td can be completely measured with a good resolution.

A simplified block diagram for such scheme is given in Fig. 3.5.2.2-5. The module can be designed on to 9U VME standard board. 32 channels in one module will be possible.

3.5.2.3 Central trigger chamber electronics

This subsystem is designed to measure the charge value carried by the output signal of central trigger chamber and to provide hit information to trigger system.

The Central Trigger Chamber will adopt a design scheme based on <optical fiber + avalanche diode>. As the signal from the avalanche diode is quite weak, a very low noise preamplifier must be designed specifically to have an acceptable S/N ratio. The design for the rest of this system can refer to one for the charge measurement of MDC.

3.5.2.4 TOF Electronics

(1)Overview

The TOF counter consists of plastic scintillator, CCT and PMTs.

The main tasks of TOF electronics are:

◊By measuring the flight time of the particles to provide the information for particle identification;

◊To provide hit information for trigger system.

◊By measuring the charge to correct the flight time.

The main measurement requirements are as follows:

◊Time measurement

Number of channels: 640

Time range: 0-60ns

Time resolution: σt ≤25ps