PREFACE

Research on nanotubes has made significant strides in a relatively short time. Reports on successful growth and characterization of carbon nanotubes are abundant. Theory and computer simulations have predicted extraordinary properties for these nanotubes. The nanotube research community is excited about a wide range of applications which has been pulling more and more researchers into the arena. The time is ripe to seriously examine the potential of this emerging field. A joint Semiconductor Research Corporation / NASA Ames Workshop was conducted at NASA Ames Research Center on November 12-13, 1998 to explore and develop long term strategy for research in nanotubes that addresses the post-100 nm needs of the microelectronics industry and the needs of the display industry. The workshop consisted of two organized sessions:

(1)Future of Nanoelectronics: evolution or revolution

(2)Nanotubes research

The workshop concluded with a discussion session to identify challenges and opportunities ahead for nanotube research. This document summarizes the outcome of the workshop and consists of the workshop announcement with the agenda, workshop report, and summary of feedback from the participants.

We wish to extend special thanks to those who worked behind the scenes to assure the success of this workshop. Special thanks goes to the Workshop Planning Committee members Prof. Hongjie Dai, Prof. Otto Zhou, Prof. Don Brenner, and Prof. John Hren. Along with colleagues from NASA Ames, Ms. Marcia Redmond and Ms. Amara

de Keczer of NASA Ames, and Ms. Sandra Church of the SRC, provided excellent administrative and logistical support. Finally, thanks to all participants for their preparation and openness during the presentations and discussions.

Dan HerrSemiconductor Research Corporation

M. MeyyappanNASA Ames Research Center

Victor ZhirnovSemiconductor Research Corporation

Workshop Announcement

SRC/NASA Ames Workshop on

Emerging Issues and Opportunities in Nanotubes and Nanoelectronics

November 1213, 1998

NASA Ames Research Center, Mountain View, CA

The Semiconductor Research Corporation (SRC) and NASA Ames Research Center have organized this workshop to explore and develop a longrange strategy for research in nanotubes that addresses the post100 nm needs of the microelectronics industry and the needs of the display industry. This workshop serves as a forum to build bridges between colleagues in the "nanotube community" and the "semiconductor community", and includes fields such as patterning, metrology, field emission, etc. The main question to be answered is: What scientific directions and results in nanotube research represent emerging and strategic breakthrough opportunities in semiconductor technology?

The aim of the workshop is twofold:

  • To educate the carbon nanotube [CNT] community on nanoscale device, materials, process, and infrastructure technology requirements incorporating perspectives from practicing engineers and industrial researchers;
  • To educate the semiconductor and related communities on the status and potential of carbon nanotubes.

The desired outcome of this workshop is a cohesive strategic plan that provides a detailed, prioritized technical agenda and timeline for collaborative research between the nanotube and semiconductor communities. This plan would include a clearly defined vision, goals, and boundary conditions for university, industry, and national laboratory research programs.

Questions and challenges include:

  • Rational design of nanotubes, correlations between structure, properties, and limits;
  • Measurements of electronic and emission properties from a single nanotube;
  • Experimental demonstration of metallic, semiconductor, and insulating behavior of nanotubes;
  • Can nanotubes be used as interconnects? Devices? Probes? Emitters?
  • Is it possible to build SingleElectron Memory based on nanotubes?
  • New circuit and chip architecture are revolutions expected?
  • Controllable and reproducible growth of nanotubes with desirable properties and helicity; (Most samples now are mixtures of single and multiwalled nanotubes with widely varying electrical properties);
  • Understanding of emission mechanism. Is this similar to diamond? Graphite?
  • Operation stability (endurance) and reliability issues;

AGENDA

Thursday, November 12, 1998

8:00 AM Registration

8.30 AM Opening Remarks: Creation of straw mission M. Meyyappan/D. Herr

9:00 AM Session I. Future of Nanoelectronics: Evolution or

Revolution ?

9:009:45 What is a device and an integrated circuit? C. Hu/UC Berkeley

Overview of ULSI devices, architecture and physics

9:4510:30 Overview of silicon microelectronics: state of the art and technology trends S. Hillenius/Lucent

10:3010:45 Break

10:4511:30 Emerging challenges in microelectronics H. Stork/HP

Includes:

Devices and Fabrication

Interconnects

Metrology/Diagnostic

Reliability problems due to high integration density

Noise due to size reduction

11:3012:15 Research Opportunities R. Doering/TI

-Fabrication of arrays of CNT diodes and transistors

-New approaches to fabrication: microtool arrays

-Demonstration of reproducibility of process and device characteristics

-Feasibility of nanotubes as interconnects

-Demonstration of feasibility of CNT nanoprobes for metrology diagnostics

-Long-term operation of CNT devices – aging effects

-Limits and trade-offs

12:151:00 Lunch

1:00 PM Session II.Nanotubes, their role in silicon microelectronics, and carbon nanotube-based nanoelectronics

1:001:30 Introduction to nanotubes B. Yacobson/RPI

1:302:00 Structural and mechanical properties of CNTs

D. Brenner/NCSU

2:002:30 Electronic and magnetic properties A. Zettl/UCBerkeley

2:303:00 Electron emission properties W. Zhu/Lucent

3:003:30Synthesis and characterization of nanotubes O. Zhou/UNCCH

3:303:45 Break

3:454:15 Patterned growth and CVD H. Dai/Stanford

4:154:45Nanolithography C. Quate/Stanford

4:455:15 Device Applications C. Dekker/Delft U. of Tech.

5:155:45Functionalization with chemical modification for metrology

R. Jaffe/NASA

5:456:00 Instruction for Session III M. Meyyappan and D. Herr

Friday, November 13, 1998

8:00 AM Session III.Discussion, Prioritization, and Consensus on Research Strategy and Agenda

12:00 Workshop Adjourns

Workshop Report

Introduction

A joint SRC/NASA Ames Workshop on Emerging Opportunities and Issues in Nanotubes and Nanoelectronics was conducted at NASA Ames Research Center, Moffett Field, in Mountain View, California on November 12 and 13, 1998. Its purpose was to explore and develop a longrange strategy for research in nanotubes that addresses the post100 nm needs of the microelectronics industry and the needs of the display industry. This workshop served as a forum to build bridges between colleagues in the "nanotube community" and the "semiconductor community,” and covered fields such as patterning, metrology, field emission, and nanoelectronics. The main question considered was: What scientific directions and results in nanotube research represent emerging and strategic breakthrough opportunities in semiconductor technology? The 54 attendees were scientists and engineers from domestic IC manufacturers, emerging nanotube supplier community, universities, and national laboratories. The high attendance reflected the importance and critical nature of the issues to the domestic semiconductor community.

The need for this workshop grew from the Grand Challenges recognized in the Semiconductor Industry Association (SIA) 1997 National Technology Roadmap for Semiconductors [NTRS], specifically:

  • The ability to continue affordable scaling;
  • Affordable lithography at and below 100 nm
  • New materials and structures;
  • Ghz frequency operation on- and off-chip;
  • Metrology and test;
  • The research and development challenge.

During the past year, the SRC and NASA Ames began a dialog on the potential of nanotube technology to address these Grand Challenges. This effort has launched several modest high risk projects with significant breakthrough potential. Based on these initial successes, this workshop focused on addressing generic, precompetitive research issues and developing an agenda for long-term university and national laboratory research on advanced nanotube materials and architectures. The desired outcome was a cohesive strategic plan that provides a detailed, prioritized technical agenda and timeline for collaborative research between the nanotube and semiconductor communities. This plan would include a clearly defined vision, goals, and boundary conditions for university, industry, and national laboratory research networks. Among the workshop’s exciting outcomes was the rapport shared by attendees and the consensus achieved regarding priority issues and a potential agenda.

Issues, Perspectives, Needs, and Opportunities

Issues, perspectives, and strategic needs and opportunities were explored in three workshop sessions, covering: (1) The future of nanoelectronics: evolution or revolution?; (2) Nanotubes, their role in silicon microelectronics, and carbon nanotubebased nanoelectronics; and (3) Discussion, prioritization, and consensus on research strategy and agenda.

The first session provided a tutorial for the carbon nanotube [CNT] community on nanoscale device, materials, process, and infrastructure technology requirements, incorporating perspectives from practicing engineers and industrial researchers, and included:

  • [C. Hu/UC Berkeley] What is a device and an integrated circuit?
  • [S. Hillenius/Lucent] Overview of silicon microelectronics: state of the art and technology trends. It may happen that the exploding cost of building future generation MOS IC fabrication facilities will be a real limitation and will slow the exponential evolution rate of silicon technology;
  • [H. Stork/HP] Emerging challenges in microelectronics: devices and fabrication, interconnects, metrology/diagnostic, reliability problems due to high integration density, and noise due to size reduction;
  • [R. Doering/TI] Research Opportunities, such as fabrication of arrays of CNT diodes and transistors; new approaches to fabrication - microtool arrays; demonstration of reproducibility of process and device characteristics; feasibility of nanotubes as interconnects; demonstration of feasibility of CNT nanoprobes for metrology diagnostics; longterm operation of CNT devices aging effects, limits and tradeoffs;

These tutorials included brief summaries of current trends in semiconductor technology and a wish list for future materials and applications. The presenters shared projected performance assumptions, timing issues, and their vision of the state-of-the-art and future developments of nanoelectronics, and discussed prospects of carbon nanotubes (CNT) for nanoelectronic devices. Most of the speakers shared the opinion that MOSFET technology will be the driving architecture through the 40 nm generation. However, they also recognized that new methods for extending CMOS into higher levels of complexity, such as selforganized processes, are highly desired and highlighted areas that represent appropriate and high-leverage research opportunities for university activity. Other general ideas conveyed by the speakers in sessions can be summarized as follows:

  • Design change is the most important issue for future microelectronics. New concepts for device architecture are required (e.g., smart routing, clockless logic, systolic arrays, selfpowered circuits etc.);
  • Since any innovations should build on the existing infrastructure, advanced development of the infrastructure (e.g., CAD etc.) to support the innovations is absolutely necessary;
  • There are several advanced designs of MOSFETs that are more appropriate for CNTbased devices (e.g., doublegated, vertical structures etc.);
  • More attention should be paid to selfassembly and other selforganizing processes, and potentially to biomolecular computing.

Specific potential opportunities and issues raised during the first session include:

  • Bulk isotropic CNTcomposites are expected to exhibit low density and could serve as a lowK dielectric insulator;
  • Highconductivity CNTs have the potential of serving as selfsupporting wires. Their inherent mechanical strength could eliminate the need for solid insulating layers;
  • Could CNTs serve as multi-micron long, nanometer diameter interconnects? This would require that a CNT film would need to be deposited, patterned and etched with techniques compatible with the underlying silicon devices. Also, techniques have yet to be discovered to manipulate and attach an individual nanotube to the lead frame. What are the electrical properties and stability of CNTs at high current densities [~106 A.cm-2?];
  • CNTs might be engineered to act as passive devices, e.g., as capacitors for DRAMs and inductors for integrated circuits in RF systems. The ability to tune and control the range of conductivity, helicity, and radii represents a significant challenge;
  • What is the potential of creating active electronic devices with CNTs? Any innovation here should meet the current standards, such as low cost (e.g., one µcent/transistor), high level of integration (e.g., 109 transistors /circuit); high reproducibility (e.g., +/ 5% tolerance for device dimensions and electrical parameters) and reliability (e.g., operating lifetime >10 years). Measuring and characterizing the timetofailure mechanisms and distributions, as functions of the significant stress parameters, represents a significant challenge;
  • Nanotubes are likely to be used as components in metrology applications which warrant small area/volume measurements of dimensions and chemical composition for diagnostics, failure analysis, and R&D purposes;
  • Niche applications: field emitters, STM tips;
  • The affordability of manufacturing with nano-tools may depend upon the simplification and integration of our traditional approach to unit processing. The feasibility of microtool arrays to address this challenge requires that they be sufficiently fast, flexible, and inexpensive. However, alternative approaches, such as chemical or biochemical based self-assembly may become competitive from an estimated cost standpoint.

Session II provided a corresponding tutorial for the semiconductor and related communities on the status and potential of carbon and related nanotubes. Topics covered included:

  • [B. Yakobson/RPI] Introduction to nanotubes;
  • [D. Brenner/NCSU] Structural and mechanical properties of CNTs;
  • [A. Zettl/UCBerkeley] Electronic and magnetic properties;
  • [W. Zhu/Lucent] Electron emission properties;
  • [O. Zhou/UNCCH] Synthesis and characterization of nanotubes;
  • [H. Dai/Stanford] Patterned growth and CVD;
  • [C. Quate/Stanford] Nanolithography;
  • [C. Dekker/Delft U. of Tech.] Device Applications;
  • [R. Jaffe/NASA Ames] Functionalization with chemical modification for metrology.

Speakers in this session summarized the state-of-the-art in theory and experiments related to nanotube research. The heavy emphasis at present on molecular models and dynamic system simulations served to highlight fundamental knowledge gaps. The need for experimental validation and a more fundamental understanding of nanotube chemistry and kinetics, rather than an empirical approach to nanotube growth, was indicated. The speakers proposed paradigm shifts in device, metrology, and patterning. Noteworthy ideas and results from these presentations include:

  • Simulation of properties: In general, the simulation results are outstanding! They suggest that CNTs may have very high electrical and thermal conductivities and ultimate mechanical strength. Electrical properties of CNTs apparently can be changed from metallic to semiconducting or insulating by varying the structure (e.g., helicity) of the CNT. In principle, devices could be fabricated from these components.
  • Fabrication: It appears unlikely that CNT technology will be inserted into device architecture and semiconductor manufacturing before the 40 nm generation. Current disadvantages of fabricating with CNTs are:

1)The temperature required for CNT growth is typically ~1200 C, which is too high to be compatible with Si technologies. Note that lower temperature CVD fabrication processes, ~500C, have been recently demonstrated. The properties of the resulting nanotubes grown at low temperatures have yet to be characterized.

2)The properties of individual CNTs synthesized in the same process can be very different.

  • Properties: Much remains to be learned about the electrical properties of CNTs. Limited results were mentioned regarding the IV characteristics of individual CNTs and their potential as semiconductors. Data on resistivity, stability at high current densities, reliability of electrical measurements, or the influence of environment on the electrical characteristics, etc. were neither presented nor discussed. Fortunately, several members of the nanotube community recognize the challenge of and need for reliable measurements.
  • Devices: A FET structure with a nanotube as a channel was discussed. However, the transistor action was not fully demonstrated as the maximum gain was only 0.35 and the output characteristic did not exhibit a saturation region, typical for MOSFETs.
  • Emitters: The electron emission properties of nanotubes were discussed. To increase the visibility of the potential of CNTs as electron emitters, the nanotube community is encouraged to present nanotube field emission results at one or more of the following conferences: International Vacuum Microelectronics Conference, International Field Emission Symposium, International Vacuum Electron Source Conference, and similar forum. This will engage other colleagues in the emitter community and facilitate dialog and feedback on the progress of nanotube technology and its relative and emerging potential as a competitive emitter technology.
  • Probes: Results on nanotubes as probes in Scanning Probe Microscopes are encouraging. Some members from semiconductor community expressed doubts about the potential of scanning probe lithography in general. Nevertheless, a demonstration of parallel array of high resolution probes (50 tips) achieved to date represents an interesting and possible breakthrough technology for addressing sub-50 nm metrology and lithography issues. Attachment of an individual CNT to a cantilever on a scanning probes represent a significant challenge. Today this is done by manipulation of individual nanotubes.
  • Customization and Functionalization: The ability to create a chemically sensitive nanoscope represents a significant advance in the state of sensor development. The importance of such an instrument at first would be for biological systems (e.g. DNA). However this capability would also be extremely important for diagnostics and addressing nanoelectronic devices and components.

Round-Table Discussion on Research Challenges and Opportunities

During the round-table discussion, participants defined a long-term agenda for research in nanotube materials, architecture, and applications. Questions and challenges raised include:

  • Growth, Structure, and Property related issues:

Understanding rate limiting growth mechanisms

  • Don’t need ‘tons a day’ but controlled and reproducible growth or patterns
  • Select chirality and grow it vs “taking whatever that comes”
  • Spaghetti-like structure vs a “3-day beard” or a “shoe-brush” on the SEM image
  • What do you do with all the catalyst particles on the substrate at the bottom of the tubes? How will this impact device operation? Can it be removed? Can the catalyst serve as a contact, e.g. Au?

Rational design of nanotubes - correlations between structure, properties, and limits;

  • Controllable and reproducible growth of nanotubes with desirable properties and helicity; (Most samples now are mixtures of single and multiwalled nanotubes with widely varying electrical properties);

Electronic Properties: